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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This header file contains identifiers and register-level core functions (or macros) that can be used to access the Xilinx HDMI TX core. </p>
<p>For more information about the operation of this core see the hardware specification and documentation in the higher level driver <a class="el" href="xv__hdmitx1_8h.html" title="This is the main header file for Xilinx HDMI TX core. ">xv_hdmitx1.h</a> file.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who    Date     Changes
</p>
<hr/>
<p>
1.00  EB     22/05/18 Initial release.
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ae801c2b02c46a84de57bc938dd96c2f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ae801c2b02c46a84de57bc938dd96c2f9">XV_HDMITX1_HW_H_</a></td></tr>
<tr class="memdesc:ae801c2b02c46a84de57bc938dd96c2f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#ae801c2b02c46a84de57bc938dd96c2f9">More...</a><br/></td></tr>
<tr class="separator:ae801c2b02c46a84de57bc938dd96c2f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abd120880a6b21ffa91223cb6c3e77af2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#abd120880a6b21ffa91223cb6c3e77af2">XV_HDMITX1_DDC_SINK_VER_REG</a>&#160;&#160;&#160;0x01</td></tr>
<tr class="memdesc:abd120880a6b21ffa91223cb6c3e77af2"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; DDC Register Address  <a href="#abd120880a6b21ffa91223cb6c3e77af2">More...</a><br/></td></tr>
<tr class="separator:abd120880a6b21ffa91223cb6c3e77af2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f2aff1ffd776d4097f3d610f92f1083"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a3f2aff1ffd776d4097f3d610f92f1083">XV_HDMITX1_DDC_CFG_1_FRL_RATE_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a3f2aff1ffd776d4097f3d610f92f1083"><td class="mdescLeft">&#160;</td><td class="mdescRight">VER (Version Interface) peripheral register offsets.  <a href="#a3f2aff1ffd776d4097f3d610f92f1083">More...</a><br/></td></tr>
<tr class="separator:a3f2aff1ffd776d4097f3d610f92f1083"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acdb9781981b55f2a70cf2ef4e50e00cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#acdb9781981b55f2a70cf2ef4e50e00cb">XV_HDMITX1_VER_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(0*4))</td></tr>
<tr class="memdesc:acdb9781981b55f2a70cf2ef4e50e00cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">VER Identification * Register offset.  <a href="#acdb9781981b55f2a70cf2ef4e50e00cb">More...</a><br/></td></tr>
<tr class="separator:acdb9781981b55f2a70cf2ef4e50e00cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab85b13706cb38b267c66b44d3533e000"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ab85b13706cb38b267c66b44d3533e000">XV_HDMITX1_VER_VERSION_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(1*4))</td></tr>
<tr class="memdesc:ab85b13706cb38b267c66b44d3533e000"><td class="mdescLeft">&#160;</td><td class="mdescRight">VER Version Register * offset.  <a href="#ab85b13706cb38b267c66b44d3533e000">More...</a><br/></td></tr>
<tr class="separator:ab85b13706cb38b267c66b44d3533e000"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3e73d02ee219e0a9c53925f60651ed78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a3e73d02ee219e0a9c53925f60651ed78">XV_HDMITX1_BRDG_FIFO_LVL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(2*4))</td></tr>
<tr class="memdesc:a3e73d02ee219e0a9c53925f60651ed78"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bridge FIFO Level Register offset.  <a href="#a3e73d02ee219e0a9c53925f60651ed78">More...</a><br/></td></tr>
<tr class="separator:a3e73d02ee219e0a9c53925f60651ed78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2a61ed968e178ed839d00ed19855ded3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a2a61ed968e178ed839d00ed19855ded3">XV_HDMITX1_VCKE_SYS_CNT_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(3*4))</td></tr>
<tr class="memdesc:a2a61ed968e178ed839d00ed19855ded3"><td class="mdescLeft">&#160;</td><td class="mdescRight">VCKE System Count Register offset.  <a href="#a2a61ed968e178ed839d00ed19855ded3">More...</a><br/></td></tr>
<tr class="separator:a2a61ed968e178ed839d00ed19855ded3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4839aca0ca1a11f8b1553026a33d8e6e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a4839aca0ca1a11f8b1553026a33d8e6e">XV_HDMITX1_DBG_STS_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(4*4))</td></tr>
<tr class="memdesc:a4839aca0ca1a11f8b1553026a33d8e6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Debug Status Register offset.  <a href="#a4839aca0ca1a11f8b1553026a33d8e6e">More...</a><br/></td></tr>
<tr class="separator:a4839aca0ca1a11f8b1553026a33d8e6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1e0129ded92751eb5637c0d3a3af7ec7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a1e0129ded92751eb5637c0d3a3af7ec7">XV_HDMITX1_ANLZ_HBP_HS_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(5*4))</td></tr>
<tr class="memdesc:a1e0129ded92751eb5637c0d3a3af7ec7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Analyzer HPB HS Register offset.  <a href="#a1e0129ded92751eb5637c0d3a3af7ec7">More...</a><br/></td></tr>
<tr class="separator:a1e0129ded92751eb5637c0d3a3af7ec7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad97a50cec14720080dc2ff6e5fd41809"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ad97a50cec14720080dc2ff6e5fd41809">XV_HDMITX1_ANLZ_LN_ACT_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(6*4))</td></tr>
<tr class="memdesc:ad97a50cec14720080dc2ff6e5fd41809"><td class="mdescLeft">&#160;</td><td class="mdescRight">Analyzer LN ACT Register offset.  <a href="#ad97a50cec14720080dc2ff6e5fd41809">More...</a><br/></td></tr>
<tr class="separator:ad97a50cec14720080dc2ff6e5fd41809"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7ce238ad43ce93c151d321b928b6909b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7ce238ad43ce93c151d321b928b6909b">XV_HDMITX1_BRDG_FIFO_LVL_MIN_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a7ce238ad43ce93c151d321b928b6909b"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 0 LTP mask.  <a href="#a7ce238ad43ce93c151d321b928b6909b">More...</a><br/></td></tr>
<tr class="separator:a7ce238ad43ce93c151d321b928b6909b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a43fbaa6f6970e192e63f4e76beb2aea2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a43fbaa6f6970e192e63f4e76beb2aea2">XV_HDMITX1_BRDG_FIFO_LVL_MIN_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a43fbaa6f6970e192e63f4e76beb2aea2"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 0 LTP shift.  <a href="#a43fbaa6f6970e192e63f4e76beb2aea2">More...</a><br/></td></tr>
<tr class="separator:a43fbaa6f6970e192e63f4e76beb2aea2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2195c02fc0a553e5d93885bb80cd5eec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a2195c02fc0a553e5d93885bb80cd5eec">XV_HDMITX1_BRDG_FIFO_LVL_MAX_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a2195c02fc0a553e5d93885bb80cd5eec"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 0 LTP mask.  <a href="#a2195c02fc0a553e5d93885bb80cd5eec">More...</a><br/></td></tr>
<tr class="separator:a2195c02fc0a553e5d93885bb80cd5eec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aee51c6675f80c84d891efc77e38bf62f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aee51c6675f80c84d891efc77e38bf62f">XV_HDMITX1_BRDG_FIFO_LVL_MAX_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:aee51c6675f80c84d891efc77e38bf62f"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 0 LTP shift.  <a href="#aee51c6675f80c84d891efc77e38bf62f">More...</a><br/></td></tr>
<tr class="separator:aee51c6675f80c84d891efc77e38bf62f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3dc6081400d3494ea259bb6edd5c1522"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a3dc6081400d3494ea259bb6edd5c1522">XV_HDMITX1_ANLZ_HBP_HS_HS_SZ_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a3dc6081400d3494ea259bb6edd5c1522"><td class="mdescLeft">&#160;</td><td class="mdescRight">Analyzer hsync size shift.  <a href="#a3dc6081400d3494ea259bb6edd5c1522">More...</a><br/></td></tr>
<tr class="separator:a3dc6081400d3494ea259bb6edd5c1522"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2a337b11e7ed5c655aaa779fcb92238e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a2a337b11e7ed5c655aaa779fcb92238e">XV_HDMITX1_ANLZ_HBP_HS_HS_SZ_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a2a337b11e7ed5c655aaa779fcb92238e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Analyzer hsync size mask.  <a href="#a2a337b11e7ed5c655aaa779fcb92238e">More...</a><br/></td></tr>
<tr class="separator:a2a337b11e7ed5c655aaa779fcb92238e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0b0c1fc1bd8023ff5443e48be1a37d52"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a0b0c1fc1bd8023ff5443e48be1a37d52">XV_HDMITX1_ANLZ_HBP_HS_HPB_SZ_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a0b0c1fc1bd8023ff5443e48be1a37d52"><td class="mdescLeft">&#160;</td><td class="mdescRight">Analyzer hbp size shift.  <a href="#a0b0c1fc1bd8023ff5443e48be1a37d52">More...</a><br/></td></tr>
<tr class="separator:a0b0c1fc1bd8023ff5443e48be1a37d52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afb2c02dfd40e7248cb5137d1fda16451"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#afb2c02dfd40e7248cb5137d1fda16451">XV_HDMITX1_ANLZ_HBP_HS_HPB_SZ_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:afb2c02dfd40e7248cb5137d1fda16451"><td class="mdescLeft">&#160;</td><td class="mdescRight">Analyzer hbp size mask.  <a href="#afb2c02dfd40e7248cb5137d1fda16451">More...</a><br/></td></tr>
<tr class="separator:afb2c02dfd40e7248cb5137d1fda16451"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a847e52c070dcb42614e10c47e6ca437b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a847e52c070dcb42614e10c47e6ca437b">XV_HDMITX1_ANLZ_LN_ACT_ACT_SZ_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a847e52c070dcb42614e10c47e6ca437b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Analyzer analyzer act size shift.  <a href="#a847e52c070dcb42614e10c47e6ca437b">More...</a><br/></td></tr>
<tr class="separator:a847e52c070dcb42614e10c47e6ca437b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab5ee2d3c0b53adc5e1baabe4bc0d8471"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ab5ee2d3c0b53adc5e1baabe4bc0d8471">XV_HDMITX1_ANLZ_LN_ACT_ACT_SZ_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:ab5ee2d3c0b53adc5e1baabe4bc0d8471"><td class="mdescLeft">&#160;</td><td class="mdescRight">Analyzer analyzer act size mask.  <a href="#ab5ee2d3c0b53adc5e1baabe4bc0d8471">More...</a><br/></td></tr>
<tr class="separator:ab5ee2d3c0b53adc5e1baabe4bc0d8471"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aecc45e839afee440ecd5c614a0f6c379"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aecc45e839afee440ecd5c614a0f6c379">XV_HDMITX1_ANLZ_LN_ACT_LN_SZ_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:aecc45e839afee440ecd5c614a0f6c379"><td class="mdescLeft">&#160;</td><td class="mdescRight">Analyzer analyzer line act shift.  <a href="#aecc45e839afee440ecd5c614a0f6c379">More...</a><br/></td></tr>
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<tr class="memitem:a553fc17abc52bfc2212f49243b910963"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a553fc17abc52bfc2212f49243b910963">XV_HDMITX1_ANLZ_LN_ACT_LN_SZ_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
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<tr class="memitem:a771c245a4146fa673670d145a49ab42c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a771c245a4146fa673670d145a49ab42c">XV_HDMITX1_PIO_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(0*4))</td></tr>
<tr class="memdesc:a771c245a4146fa673670d145a49ab42c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Identification * Register offset.  <a href="#a771c245a4146fa673670d145a49ab42c">More...</a><br/></td></tr>
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<tr class="memitem:aac3a70c2cfaeaee8e5b85888bcaa38d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aac3a70c2cfaeaee8e5b85888bcaa38d3">XV_HDMITX1_PIO_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(1*4))</td></tr>
<tr class="memdesc:aac3a70c2cfaeaee8e5b85888bcaa38d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Register * offset.  <a href="#aac3a70c2cfaeaee8e5b85888bcaa38d3">More...</a><br/></td></tr>
<tr class="separator:aac3a70c2cfaeaee8e5b85888bcaa38d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7b92bd89968718f069ca23ff200f90b0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7b92bd89968718f069ca23ff200f90b0">XV_HDMITX1_PIO_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(2*4))</td></tr>
<tr class="memdesc:a7b92bd89968718f069ca23ff200f90b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Register Set * offset.  <a href="#a7b92bd89968718f069ca23ff200f90b0">More...</a><br/></td></tr>
<tr class="separator:a7b92bd89968718f069ca23ff200f90b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab2c8c843f94dae2bf7b7050da886ee8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ab2c8c843f94dae2bf7b7050da886ee8f">XV_HDMITX1_PIO_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(3*4))</td></tr>
<tr class="memdesc:ab2c8c843f94dae2bf7b7050da886ee8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Register Clear * offset.  <a href="#ab2c8c843f94dae2bf7b7050da886ee8f">More...</a><br/></td></tr>
<tr class="separator:ab2c8c843f94dae2bf7b7050da886ee8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aad716fe9cadcb6ad07df46c18b0f67d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aad716fe9cadcb6ad07df46c18b0f67d9">XV_HDMITX1_PIO_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(4*4))</td></tr>
<tr class="memdesc:aad716fe9cadcb6ad07df46c18b0f67d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Status Register * offset.  <a href="#aad716fe9cadcb6ad07df46c18b0f67d9">More...</a><br/></td></tr>
<tr class="separator:aad716fe9cadcb6ad07df46c18b0f67d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aef14faec6d7dec76359597de87c027e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aef14faec6d7dec76359597de87c027e1">XV_HDMITX1_PIO_OUT_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(5*4))</td></tr>
<tr class="memdesc:aef14faec6d7dec76359597de87c027e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register offset.  <a href="#aef14faec6d7dec76359597de87c027e1">More...</a><br/></td></tr>
<tr class="separator:aef14faec6d7dec76359597de87c027e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a916d49f0a22d9ef6e369ff80353e00af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(6*4))</td></tr>
<tr class="memdesc:a916d49f0a22d9ef6e369ff80353e00af"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register Set * offset.  <a href="#a916d49f0a22d9ef6e369ff80353e00af">More...</a><br/></td></tr>
<tr class="separator:a916d49f0a22d9ef6e369ff80353e00af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a34819a1c42353de5eec449bc38c93efc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(7*4))</td></tr>
<tr class="memdesc:a34819a1c42353de5eec449bc38c93efc"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register Clear * offset.  <a href="#a34819a1c42353de5eec449bc38c93efc">More...</a><br/></td></tr>
<tr class="separator:a34819a1c42353de5eec449bc38c93efc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae9de0ab9551b81695551dd340024f11a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ae9de0ab9551b81695551dd340024f11a">XV_HDMITX1_PIO_OUT_MSK_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(8*4))</td></tr>
<tr class="memdesc:ae9de0ab9551b81695551dd340024f11a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Mask Register * offset.  <a href="#ae9de0ab9551b81695551dd340024f11a">More...</a><br/></td></tr>
<tr class="separator:ae9de0ab9551b81695551dd340024f11a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab20b6e84abcd0378fbc8e17282eacb16"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ab20b6e84abcd0378fbc8e17282eacb16">XV_HDMITX1_PIO_IN_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(9*4))</td></tr>
<tr class="memdesc:ab20b6e84abcd0378fbc8e17282eacb16"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Register offset.  <a href="#ab20b6e84abcd0378fbc8e17282eacb16">More...</a><br/></td></tr>
<tr class="separator:ab20b6e84abcd0378fbc8e17282eacb16"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aae6c35fd65f989a9a2002d0b5d1fb456"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aae6c35fd65f989a9a2002d0b5d1fb456">XV_HDMITX1_PIO_IN_EVT_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(10*4))</td></tr>
<tr class="memdesc:aae6c35fd65f989a9a2002d0b5d1fb456"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Register * offset.  <a href="#aae6c35fd65f989a9a2002d0b5d1fb456">More...</a><br/></td></tr>
<tr class="separator:aae6c35fd65f989a9a2002d0b5d1fb456"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a083e42899636cd5e11e57dc81ed473d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a083e42899636cd5e11e57dc81ed473d1">XV_HDMITX1_PIO_IN_EVT_RE_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(11*4))</td></tr>
<tr class="memdesc:a083e42899636cd5e11e57dc81ed473d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Rising Edge Register offset.  <a href="#a083e42899636cd5e11e57dc81ed473d1">More...</a><br/></td></tr>
<tr class="separator:a083e42899636cd5e11e57dc81ed473d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0840f8be0f908f0ebf7f88da62919041"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a0840f8be0f908f0ebf7f88da62919041">XV_HDMITX1_PIO_IN_EVT_FE_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(12*4))</td></tr>
<tr class="memdesc:a0840f8be0f908f0ebf7f88da62919041"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Falling Edge Register offset.  <a href="#a0840f8be0f908f0ebf7f88da62919041">More...</a><br/></td></tr>
<tr class="separator:a0840f8be0f908f0ebf7f88da62919041"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8239e53495feea5050dbda9cad646119"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a8239e53495feea5050dbda9cad646119">XV_HDMITX1_HPD_TIMEGRID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(13*4))</td></tr>
<tr class="memdesc:a8239e53495feea5050dbda9cad646119"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO HPD Config.  <a href="#a8239e53495feea5050dbda9cad646119">More...</a><br/></td></tr>
<tr class="separator:a8239e53495feea5050dbda9cad646119"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3154f6e901d66ba2320ccf5ab4d08821"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a3154f6e901d66ba2320ccf5ab4d08821">XV_HDMITX1_TOGGLE_CONF_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(14*4))</td></tr>
<tr class="memdesc:a3154f6e901d66ba2320ccf5ab4d08821"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO HPD Config.  <a href="#a3154f6e901d66ba2320ccf5ab4d08821">More...</a><br/></td></tr>
<tr class="separator:a3154f6e901d66ba2320ccf5ab4d08821"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5f8f27b07f3e43e7bf04c5bda2e1179f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a5f8f27b07f3e43e7bf04c5bda2e1179f">XV_HDMITX1_CONNECT_CONF_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(15*4))</td></tr>
<tr class="memdesc:a5f8f27b07f3e43e7bf04c5bda2e1179f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO HPD Config.  <a href="#a5f8f27b07f3e43e7bf04c5bda2e1179f">More...</a><br/></td></tr>
<tr class="separator:a5f8f27b07f3e43e7bf04c5bda2e1179f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7dbedee4c4749f3d28da3b493c792cb6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7dbedee4c4749f3d28da3b493c792cb6">XV_HDMITX1_PIO_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a7dbedee4c4749f3d28da3b493c792cb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Run mask.  <a href="#a7dbedee4c4749f3d28da3b493c792cb6">More...</a><br/></td></tr>
<tr class="separator:a7dbedee4c4749f3d28da3b493c792cb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a633284b6032afb987ebdc09d68e111a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a633284b6032afb987ebdc09d68e111a5">XV_HDMITX1_PIO_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a633284b6032afb987ebdc09d68e111a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Interrupt Enable mask.  <a href="#a633284b6032afb987ebdc09d68e111a5">More...</a><br/></td></tr>
<tr class="separator:a633284b6032afb987ebdc09d68e111a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab68b9045690c17f85d3d454f182aaaa4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ab68b9045690c17f85d3d454f182aaaa4">XV_HDMITX1_PIO_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:ab68b9045690c17f85d3d454f182aaaa4"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Status Interrupt mask.  <a href="#ab68b9045690c17f85d3d454f182aaaa4">More...</a><br/></td></tr>
<tr class="separator:ab68b9045690c17f85d3d454f182aaaa4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77a89d53c2da8e5b11717d4ddb29da32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a77a89d53c2da8e5b11717d4ddb29da32">XV_HDMITX1_PIO_STA_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a77a89d53c2da8e5b11717d4ddb29da32"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Status Event mask.  <a href="#a77a89d53c2da8e5b11717d4ddb29da32">More...</a><br/></td></tr>
<tr class="separator:a77a89d53c2da8e5b11717d4ddb29da32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a01feb7322f445f662f190d24c4d82583"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a01feb7322f445f662f190d24c4d82583">XV_HDMITX1_PIO_OUT_RST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a01feb7322f445f662f190d24c4d82583"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Reset mask.  <a href="#a01feb7322f445f662f190d24c4d82583">More...</a><br/></td></tr>
<tr class="separator:a01feb7322f445f662f190d24c4d82583"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4ce35ba56d898dd0b26cc1466d7ff9e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a4ce35ba56d898dd0b26cc1466d7ff9e6">XV_HDMITX1_PIO_OUT_MODE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a4ce35ba56d898dd0b26cc1466d7ff9e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Mode mask.  <a href="#a4ce35ba56d898dd0b26cc1466d7ff9e6">More...</a><br/></td></tr>
<tr class="separator:a4ce35ba56d898dd0b26cc1466d7ff9e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a58610b772b050b3a4504d274bd53f09a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a58610b772b050b3a4504d274bd53f09a">XV_HDMITX1_PIO_OUT_COLOR_DEPTH_MASK</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:a58610b772b050b3a4504d274bd53f09a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Depth mask.  <a href="#a58610b772b050b3a4504d274bd53f09a">More...</a><br/></td></tr>
<tr class="separator:a58610b772b050b3a4504d274bd53f09a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a493cc4bcc9456c6e4b5b7b6f4ef278c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a493cc4bcc9456c6e4b5b7b6f4ef278c7">XV_HDMITX1_PIO_OUT_PIXEL_RATE_MASK</a>&#160;&#160;&#160;0xC0</td></tr>
<tr class="memdesc:a493cc4bcc9456c6e4b5b7b6f4ef278c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Pixel Rate mask.  <a href="#a493cc4bcc9456c6e4b5b7b6f4ef278c7">More...</a><br/></td></tr>
<tr class="separator:a493cc4bcc9456c6e4b5b7b6f4ef278c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a36e3a208b0ef9f5385c89a994916c49c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a36e3a208b0ef9f5385c89a994916c49c">XV_HDMITX1_PIO_OUT_SAMPLE_RATE_MASK</a>&#160;&#160;&#160;0x300</td></tr>
<tr class="memdesc:a36e3a208b0ef9f5385c89a994916c49c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Sample Rate mask.  <a href="#a36e3a208b0ef9f5385c89a994916c49c">More...</a><br/></td></tr>
<tr class="separator:a36e3a208b0ef9f5385c89a994916c49c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac9a6bae49a6bba1d495a19e74aff47d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ac9a6bae49a6bba1d495a19e74aff47d8">XV_HDMITX1_PIO_OUT_COLOR_SPACE_MASK</a>&#160;&#160;&#160;0xC00</td></tr>
<tr class="memdesc:ac9a6bae49a6bba1d495a19e74aff47d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Space mask.  <a href="#ac9a6bae49a6bba1d495a19e74aff47d8">More...</a><br/></td></tr>
<tr class="separator:ac9a6bae49a6bba1d495a19e74aff47d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa6ac2799e1faa5133f3ab35018aba54d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aa6ac2799e1faa5133f3ab35018aba54d">XV_HDMITX1_PIO_OUT_SCRM_MASK</a>&#160;&#160;&#160;(1&lt;&lt;12)</td></tr>
<tr class="memdesc:aa6ac2799e1faa5133f3ab35018aba54d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Scrambler mask.  <a href="#aa6ac2799e1faa5133f3ab35018aba54d">More...</a><br/></td></tr>
<tr class="separator:aa6ac2799e1faa5133f3ab35018aba54d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9044e4c1c1a22e9f5540b3e28e164ebe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a9044e4c1c1a22e9f5540b3e28e164ebe">XV_HDMITX1_PIO_OUT_COLOR_DEPTH_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:a9044e4c1c1a22e9f5540b3e28e164ebe"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Depth shift.  <a href="#a9044e4c1c1a22e9f5540b3e28e164ebe">More...</a><br/></td></tr>
<tr class="separator:a9044e4c1c1a22e9f5540b3e28e164ebe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6fe7c0047c787b5b463931d65a9857aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a6fe7c0047c787b5b463931d65a9857aa">XV_HDMITX1_PIO_OUT_PIXEL_RATE_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:a6fe7c0047c787b5b463931d65a9857aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Pixel Rate shift.  <a href="#a6fe7c0047c787b5b463931d65a9857aa">More...</a><br/></td></tr>
<tr class="separator:a6fe7c0047c787b5b463931d65a9857aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab23dda9e51f0e85b00f859790bce3ad4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ab23dda9e51f0e85b00f859790bce3ad4">XV_HDMITX1_PIO_OUT_SAMPLE_RATE_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ab23dda9e51f0e85b00f859790bce3ad4"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Sample Rate shift.  <a href="#ab23dda9e51f0e85b00f859790bce3ad4">More...</a><br/></td></tr>
<tr class="separator:ab23dda9e51f0e85b00f859790bce3ad4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aef681ccbd7dad5067f84ef4b7ecdc685"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aef681ccbd7dad5067f84ef4b7ecdc685">XV_HDMITX1_PIO_OUT_COLOR_SPACE_SHIFT</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:aef681ccbd7dad5067f84ef4b7ecdc685"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Space shift.  <a href="#aef681ccbd7dad5067f84ef4b7ecdc685">More...</a><br/></td></tr>
<tr class="separator:aef681ccbd7dad5067f84ef4b7ecdc685"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af12c5bc4580008e386420488c4dc2945"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#af12c5bc4580008e386420488c4dc2945">XV_HDMITX1_PIO_OUT_GCP_CLEARAVMUTE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;28)</td></tr>
<tr class="memdesc:af12c5bc4580008e386420488c4dc2945"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out GCP_CLEARAVMUTE mask.  <a href="#af12c5bc4580008e386420488c4dc2945">More...</a><br/></td></tr>
<tr class="separator:af12c5bc4580008e386420488c4dc2945"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afcb960eb73caed51fff7e1028e0d3a11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#afcb960eb73caed51fff7e1028e0d3a11">XV_HDMITX1_PIO_OUT_BRIDGE_YUV420_MASK</a>&#160;&#160;&#160;(1&lt;&lt;29)</td></tr>
<tr class="memdesc:afcb960eb73caed51fff7e1028e0d3a11"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Bridge_YUV420 mask.  <a href="#afcb960eb73caed51fff7e1028e0d3a11">More...</a><br/></td></tr>
<tr class="separator:afcb960eb73caed51fff7e1028e0d3a11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a648102aabd55a2e9475005867d63dd6e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a648102aabd55a2e9475005867d63dd6e">XV_HDMITX1_PIO_OUT_BRIDGE_PIXEL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;30)</td></tr>
<tr class="memdesc:a648102aabd55a2e9475005867d63dd6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Bridge_Pixel repeat mask.  <a href="#a648102aabd55a2e9475005867d63dd6e">More...</a><br/></td></tr>
<tr class="separator:a648102aabd55a2e9475005867d63dd6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acdf644126236c17fe0561f8b7b35e848"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#acdf644126236c17fe0561f8b7b35e848">XV_HDMITX1_PIO_OUT_GCP_AVMUTE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;31)</td></tr>
<tr class="memdesc:acdf644126236c17fe0561f8b7b35e848"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out GCP_AVMUTE mask.  <a href="#acdf644126236c17fe0561f8b7b35e848">More...</a><br/></td></tr>
<tr class="separator:acdf644126236c17fe0561f8b7b35e848"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abb0a513439f7691a66e0baba33ee7e99"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#abb0a513439f7691a66e0baba33ee7e99">XV_HDMITX1_PIO_OUT_INT_VRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:abb0a513439f7691a66e0baba33ee7e99"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out INT_VRST mask.  <a href="#abb0a513439f7691a66e0baba33ee7e99">More...</a><br/></td></tr>
<tr class="separator:abb0a513439f7691a66e0baba33ee7e99"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae926811c3ab955754b7e1d34e06c0b30"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ae926811c3ab955754b7e1d34e06c0b30">XV_HDMITX1_PIO_OUT_INT_LRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;20)</td></tr>
<tr class="memdesc:ae926811c3ab955754b7e1d34e06c0b30"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out INT_LRST mask.  <a href="#ae926811c3ab955754b7e1d34e06c0b30">More...</a><br/></td></tr>
<tr class="separator:ae926811c3ab955754b7e1d34e06c0b30"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0ef4633d186e31591484e815f99ef471"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a0ef4633d186e31591484e815f99ef471">XV_HDMITX1_PIO_OUT_EXT_VRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;21)</td></tr>
<tr class="memdesc:a0ef4633d186e31591484e815f99ef471"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out EXT_VRST mask.  <a href="#a0ef4633d186e31591484e815f99ef471">More...</a><br/></td></tr>
<tr class="separator:a0ef4633d186e31591484e815f99ef471"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a11a55e987433d85234ed12bbaeae13ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a11a55e987433d85234ed12bbaeae13ad">XV_HDMITX1_PIO_OUT_EXT_SYSRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;22)</td></tr>
<tr class="memdesc:a11a55e987433d85234ed12bbaeae13ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out EXT_SYSRST mask.  <a href="#a11a55e987433d85234ed12bbaeae13ad">More...</a><br/></td></tr>
<tr class="separator:a11a55e987433d85234ed12bbaeae13ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abe4e12802e1167c1761c54d00083dad6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#abe4e12802e1167c1761c54d00083dad6">XV_HDMITX1_PIO_OUT_DYN_HDR_DM_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 23)</td></tr>
<tr class="memdesc:abe4e12802e1167c1761c54d00083dad6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Dynamic HDR Data Mover Enable.  <a href="#abe4e12802e1167c1761c54d00083dad6">More...</a><br/></td></tr>
<tr class="separator:abe4e12802e1167c1761c54d00083dad6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9c67bb4f654071b9bbd7c0bb57bd431b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a9c67bb4f654071b9bbd7c0bb57bd431b">XV_HDMITX1_PIO_IN_LNK_RDY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a9c67bb4f654071b9bbd7c0bb57bd431b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In link ready mask.  <a href="#a9c67bb4f654071b9bbd7c0bb57bd431b">More...</a><br/></td></tr>
<tr class="separator:a9c67bb4f654071b9bbd7c0bb57bd431b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9535ee8b4bd5af9bd9b91476b2ccfec5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a9535ee8b4bd5af9bd9b91476b2ccfec5">XV_HDMITX1_PIO_IN_VID_RDY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a9535ee8b4bd5af9bd9b91476b2ccfec5"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In video ready mask.  <a href="#a9535ee8b4bd5af9bd9b91476b2ccfec5">More...</a><br/></td></tr>
<tr class="separator:a9535ee8b4bd5af9bd9b91476b2ccfec5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8e4ab9f93df19e5011f0abc4b62d6d68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a8e4ab9f93df19e5011f0abc4b62d6d68">XV_HDMITX1_PIO_IN_HPD_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a8e4ab9f93df19e5011f0abc4b62d6d68"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In HPD mask.  <a href="#a8e4ab9f93df19e5011f0abc4b62d6d68">More...</a><br/></td></tr>
<tr class="separator:a8e4ab9f93df19e5011f0abc4b62d6d68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa69dc4de1fcc61075bb66a5f72498f09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aa69dc4de1fcc61075bb66a5f72498f09">XV_HDMITX1_PIO_IN_VS_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:aa69dc4de1fcc61075bb66a5f72498f09"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Vsync mask.  <a href="#aa69dc4de1fcc61075bb66a5f72498f09">More...</a><br/></td></tr>
<tr class="separator:aa69dc4de1fcc61075bb66a5f72498f09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0ebc15cfa04faafb28f8ffbf75ae033a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a0ebc15cfa04faafb28f8ffbf75ae033a">XV_HDMITX1_PIO_IN_PPP_MASK</a>&#160;&#160;&#160;0x07</td></tr>
<tr class="memdesc:a0ebc15cfa04faafb28f8ffbf75ae033a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Pixel packing phase mask.  <a href="#a0ebc15cfa04faafb28f8ffbf75ae033a">More...</a><br/></td></tr>
<tr class="separator:a0ebc15cfa04faafb28f8ffbf75ae033a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acaa33be8f32fd160bc231fe83d8e4e7b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#acaa33be8f32fd160bc231fe83d8e4e7b">XV_HDMITX1_PIO_IN_HPD_TOGGLE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:acaa33be8f32fd160bc231fe83d8e4e7b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In HPD toggle mask.  <a href="#acaa33be8f32fd160bc231fe83d8e4e7b">More...</a><br/></td></tr>
<tr class="separator:acaa33be8f32fd160bc231fe83d8e4e7b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada3d9d45b3dfcc1f6ed0bf48ee626a4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ada3d9d45b3dfcc1f6ed0bf48ee626a4b">XV_HDMITX1_PIO_IN_PPP_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ada3d9d45b3dfcc1f6ed0bf48ee626a4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Pixel packing phase shift.  <a href="#ada3d9d45b3dfcc1f6ed0bf48ee626a4b">More...</a><br/></td></tr>
<tr class="separator:ada3d9d45b3dfcc1f6ed0bf48ee626a4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a47d0be5976cb417367f227882aba616a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a47d0be5976cb417367f227882aba616a">XV_HDMITX1_PIO_IN_BRDG_LOCKED_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:a47d0be5976cb417367f227882aba616a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Bridge Locked mask.  <a href="#a47d0be5976cb417367f227882aba616a">More...</a><br/></td></tr>
<tr class="separator:a47d0be5976cb417367f227882aba616a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad7989878b63e6d1ccc17b9fffebdb1e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ad7989878b63e6d1ccc17b9fffebdb1e7">XV_HDMITX1_PIO_IN_BRDG_OVERFLOW_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:ad7989878b63e6d1ccc17b9fffebdb1e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Bridge Overflow mask.  <a href="#ad7989878b63e6d1ccc17b9fffebdb1e7">More...</a><br/></td></tr>
<tr class="separator:ad7989878b63e6d1ccc17b9fffebdb1e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d53bbc6e4513d332030da84a4d5366c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a9d53bbc6e4513d332030da84a4d5366c">XV_HDMITX1_PIO_IN_BRDG_UNDERFLOW_MASK</a>&#160;&#160;&#160;(1&lt;&lt;11)</td></tr>
<tr class="memdesc:a9d53bbc6e4513d332030da84a4d5366c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Bridge Underflow mask.  <a href="#a9d53bbc6e4513d332030da84a4d5366c">More...</a><br/></td></tr>
<tr class="separator:a9d53bbc6e4513d332030da84a4d5366c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2fd4e57b08325f9c9b9a65efa90866cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a2fd4e57b08325f9c9b9a65efa90866cf">XV_HDMITX1_DDC_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(0*4))</td></tr>
<tr class="memdesc:a2fd4e57b08325f9c9b9a65efa90866cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Identification * Register offset.  <a href="#a2fd4e57b08325f9c9b9a65efa90866cf">More...</a><br/></td></tr>
<tr class="separator:a2fd4e57b08325f9c9b9a65efa90866cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a446a4adab4ed3b06eb0834191bfa15d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a446a4adab4ed3b06eb0834191bfa15d9">XV_HDMITX1_DDC_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(1*4))</td></tr>
<tr class="memdesc:a446a4adab4ed3b06eb0834191bfa15d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register * offset.  <a href="#a446a4adab4ed3b06eb0834191bfa15d9">More...</a><br/></td></tr>
<tr class="separator:a446a4adab4ed3b06eb0834191bfa15d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a07043f2b7e7ddb3ba0f27b893e938ed2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a07043f2b7e7ddb3ba0f27b893e938ed2">XV_HDMITX1_DDC_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(2*4))</td></tr>
<tr class="memdesc:a07043f2b7e7ddb3ba0f27b893e938ed2"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register Set * offset.  <a href="#a07043f2b7e7ddb3ba0f27b893e938ed2">More...</a><br/></td></tr>
<tr class="separator:a07043f2b7e7ddb3ba0f27b893e938ed2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a09105460882cbec545e9ef4fa49b72ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a09105460882cbec545e9ef4fa49b72ae">XV_HDMITX1_DDC_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(3*4))</td></tr>
<tr class="memdesc:a09105460882cbec545e9ef4fa49b72ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register Clear * offset.  <a href="#a09105460882cbec545e9ef4fa49b72ae">More...</a><br/></td></tr>
<tr class="separator:a09105460882cbec545e9ef4fa49b72ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a76a8d1762bfc7aafed3ae667630f47d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a76a8d1762bfc7aafed3ae667630f47d6">XV_HDMITX1_DDC_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(4*4))</td></tr>
<tr class="memdesc:a76a8d1762bfc7aafed3ae667630f47d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Register * offset.  <a href="#a76a8d1762bfc7aafed3ae667630f47d6">More...</a><br/></td></tr>
<tr class="separator:a76a8d1762bfc7aafed3ae667630f47d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a96820760e1aae244998532830dd393fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a96820760e1aae244998532830dd393fa">XV_HDMITX1_DDC_CMD_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(5*4))</td></tr>
<tr class="memdesc:a96820760e1aae244998532830dd393fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Command Register * offset.  <a href="#a96820760e1aae244998532830dd393fa">More...</a><br/></td></tr>
<tr class="separator:a96820760e1aae244998532830dd393fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afaa80a0d738dde8b78bf9eff80002872"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#afaa80a0d738dde8b78bf9eff80002872">XV_HDMITX1_DDC_DAT_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(6*4))</td></tr>
<tr class="memdesc:afaa80a0d738dde8b78bf9eff80002872"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Data Register * offset.  <a href="#afaa80a0d738dde8b78bf9eff80002872">More...</a><br/></td></tr>
<tr class="separator:afaa80a0d738dde8b78bf9eff80002872"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7ff97e413ac155c87891bc822fa79213"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7ff97e413ac155c87891bc822fa79213">XV_HDMITX1_DDC_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a7ff97e413ac155c87891bc822fa79213"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Run mask.  <a href="#a7ff97e413ac155c87891bc822fa79213">More...</a><br/></td></tr>
<tr class="separator:a7ff97e413ac155c87891bc822fa79213"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5eb95f04ded48dfbc6d9b1895d86ba6e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a5eb95f04ded48dfbc6d9b1895d86ba6e">XV_HDMITX1_DDC_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a5eb95f04ded48dfbc6d9b1895d86ba6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Interrupt Enable mask.  <a href="#a5eb95f04ded48dfbc6d9b1895d86ba6e">More...</a><br/></td></tr>
<tr class="separator:a5eb95f04ded48dfbc6d9b1895d86ba6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a859fcc36dfd9528cb0cf13e2053fefd1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a859fcc36dfd9528cb0cf13e2053fefd1">XV_HDMITX1_DDC_CTRL_TO_STOP_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a859fcc36dfd9528cb0cf13e2053fefd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control TO Stop mask.  <a href="#a859fcc36dfd9528cb0cf13e2053fefd1">More...</a><br/></td></tr>
<tr class="separator:a859fcc36dfd9528cb0cf13e2053fefd1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac2f786b3061b4df4c53544b6e90f9644"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ac2f786b3061b4df4c53544b6e90f9644">XV_HDMITX1_DDC_CTRL_CLK_DIV_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:ac2f786b3061b4df4c53544b6e90f9644"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Clock Divider mask.  <a href="#ac2f786b3061b4df4c53544b6e90f9644">More...</a><br/></td></tr>
<tr class="separator:ac2f786b3061b4df4c53544b6e90f9644"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74458333d15b366f123b04bb3fa44042"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a74458333d15b366f123b04bb3fa44042">XV_HDMITX1_DDC_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a74458333d15b366f123b04bb3fa44042"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status IRQ mask.  <a href="#a74458333d15b366f123b04bb3fa44042">More...</a><br/></td></tr>
<tr class="separator:a74458333d15b366f123b04bb3fa44042"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a13677e2d21fd6fda67136dde0657b511"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a13677e2d21fd6fda67136dde0657b511">XV_HDMITX1_DDC_STA_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a13677e2d21fd6fda67136dde0657b511"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Event mask.  <a href="#a13677e2d21fd6fda67136dde0657b511">More...</a><br/></td></tr>
<tr class="separator:a13677e2d21fd6fda67136dde0657b511"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afbe726446602f7316ba9f98aabf0541f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#afbe726446602f7316ba9f98aabf0541f">XV_HDMITX1_DDC_STA_BUSY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:afbe726446602f7316ba9f98aabf0541f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Busy mask.  <a href="#afbe726446602f7316ba9f98aabf0541f">More...</a><br/></td></tr>
<tr class="separator:afbe726446602f7316ba9f98aabf0541f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0e2070bd8eb10e5ab04afd78224a7c7f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a0e2070bd8eb10e5ab04afd78224a7c7f">XV_HDMITX1_DDC_STA_DONE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a0e2070bd8eb10e5ab04afd78224a7c7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Busy mask.  <a href="#a0e2070bd8eb10e5ab04afd78224a7c7f">More...</a><br/></td></tr>
<tr class="separator:a0e2070bd8eb10e5ab04afd78224a7c7f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa139f217587a626986768317c2efb5e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aa139f217587a626986768317c2efb5e3">XV_HDMITX1_DDC_STA_TIMEOUT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:aa139f217587a626986768317c2efb5e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Timeout mask.  <a href="#aa139f217587a626986768317c2efb5e3">More...</a><br/></td></tr>
<tr class="separator:aa139f217587a626986768317c2efb5e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a18917060714340b40a33de19976226"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7a18917060714340b40a33de19976226">XV_HDMITX1_DDC_STA_ACK_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:a7a18917060714340b40a33de19976226"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status ACK mask.  <a href="#a7a18917060714340b40a33de19976226">More...</a><br/></td></tr>
<tr class="separator:a7a18917060714340b40a33de19976226"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab727e3b036b6253c5ce50aa6a219c203"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ab727e3b036b6253c5ce50aa6a219c203">XV_HDMITX1_DDC_STA_SCL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:ab727e3b036b6253c5ce50aa6a219c203"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC State of SCL Input mask.  <a href="#ab727e3b036b6253c5ce50aa6a219c203">More...</a><br/></td></tr>
<tr class="separator:ab727e3b036b6253c5ce50aa6a219c203"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aac90959218c9a9cf4c414d457508182f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aac90959218c9a9cf4c414d457508182f">XV_HDMITX1_DDC_STA_SDA_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:aac90959218c9a9cf4c414d457508182f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC State of SDA Input mask.  <a href="#aac90959218c9a9cf4c414d457508182f">More...</a><br/></td></tr>
<tr class="separator:aac90959218c9a9cf4c414d457508182f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a332860dddbc7497d6cf29f5d9fd7b247"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a332860dddbc7497d6cf29f5d9fd7b247">XV_HDMITX1_DDC_STA_CMD_FULL</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:a332860dddbc7497d6cf29f5d9fd7b247"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command fifo full.  <a href="#a332860dddbc7497d6cf29f5d9fd7b247">More...</a><br/></td></tr>
<tr class="separator:a332860dddbc7497d6cf29f5d9fd7b247"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af92b02d943db10c03bd66537c4b73e3d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#af92b02d943db10c03bd66537c4b73e3d">XV_HDMITX1_DDC_STA_DAT_EMPTY</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:af92b02d943db10c03bd66537c4b73e3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data fifo empty.  <a href="#af92b02d943db10c03bd66537c4b73e3d">More...</a><br/></td></tr>
<tr class="separator:af92b02d943db10c03bd66537c4b73e3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5b8cad2a23958c491543b26339bf1476"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a5b8cad2a23958c491543b26339bf1476">XV_HDMITX1_DDC_STA_CMD_WRDS_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:a5b8cad2a23958c491543b26339bf1476"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command fifo words mask.  <a href="#a5b8cad2a23958c491543b26339bf1476">More...</a><br/></td></tr>
<tr class="separator:a5b8cad2a23958c491543b26339bf1476"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a76f3d0e0be126d1b261c496067ef61ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a76f3d0e0be126d1b261c496067ef61ee">XV_HDMITX1_DDC_STA_CMD_WRDS_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a76f3d0e0be126d1b261c496067ef61ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command fifo words shift.  <a href="#a76f3d0e0be126d1b261c496067ef61ee">More...</a><br/></td></tr>
<tr class="separator:a76f3d0e0be126d1b261c496067ef61ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a657d709c24bab4058ec2172a8ffcb056"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a657d709c24bab4058ec2172a8ffcb056">XV_HDMITX1_DDC_STA_DAT_WRDS_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:a657d709c24bab4058ec2172a8ffcb056"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data fifo words mask.  <a href="#a657d709c24bab4058ec2172a8ffcb056">More...</a><br/></td></tr>
<tr class="separator:a657d709c24bab4058ec2172a8ffcb056"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa18c60108ec297b2f5cb6d201bb880ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aa18c60108ec297b2f5cb6d201bb880ad">XV_HDMITX1_DDC_STA_DAT_WRDS_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:aa18c60108ec297b2f5cb6d201bb880ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data fifo words shift.  <a href="#aa18c60108ec297b2f5cb6d201bb880ad">More...</a><br/></td></tr>
<tr class="separator:aa18c60108ec297b2f5cb6d201bb880ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a845b5618c93a1561f1a0a14c8f3eff8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a845b5618c93a1561f1a0a14c8f3eff8e">XV_HDMITX1_DDC_CMD_STR_TOKEN</a>&#160;&#160;&#160;(0x100)</td></tr>
<tr class="memdesc:a845b5618c93a1561f1a0a14c8f3eff8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start token.  <a href="#a845b5618c93a1561f1a0a14c8f3eff8e">More...</a><br/></td></tr>
<tr class="separator:a845b5618c93a1561f1a0a14c8f3eff8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac055e0da09799cd2bf1deaaf7d594a9b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ac055e0da09799cd2bf1deaaf7d594a9b">XV_HDMITX1_DDC_CMD_STP_TOKEN</a>&#160;&#160;&#160;(0x101)</td></tr>
<tr class="memdesc:ac055e0da09799cd2bf1deaaf7d594a9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop token.  <a href="#ac055e0da09799cd2bf1deaaf7d594a9b">More...</a><br/></td></tr>
<tr class="separator:ac055e0da09799cd2bf1deaaf7d594a9b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7c6cd9c2d19d95db83b737e22375377a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7c6cd9c2d19d95db83b737e22375377a">XV_HDMITX1_DDC_CMD_RD_TOKEN</a>&#160;&#160;&#160;(0x102)</td></tr>
<tr class="memdesc:a7c6cd9c2d19d95db83b737e22375377a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read token.  <a href="#a7c6cd9c2d19d95db83b737e22375377a">More...</a><br/></td></tr>
<tr class="separator:a7c6cd9c2d19d95db83b737e22375377a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a138fe51f7ce3717cfaf38b3a67098566"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a138fe51f7ce3717cfaf38b3a67098566">XV_HDMITX1_DDC_CMD_WR_TOKEN</a>&#160;&#160;&#160;(0x103)</td></tr>
<tr class="memdesc:a138fe51f7ce3717cfaf38b3a67098566"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write token.  <a href="#a138fe51f7ce3717cfaf38b3a67098566">More...</a><br/></td></tr>
<tr class="separator:a138fe51f7ce3717cfaf38b3a67098566"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74ffbd378e3b8593508795e42350a66b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a74ffbd378e3b8593508795e42350a66b">XV_HDMITX1_AUX_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(0*4))</td></tr>
<tr class="memdesc:a74ffbd378e3b8593508795e42350a66b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Identification * Register offset.  <a href="#a74ffbd378e3b8593508795e42350a66b">More...</a><br/></td></tr>
<tr class="separator:a74ffbd378e3b8593508795e42350a66b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a50a0ddd2870cfaa6f8354b6c9bd05682"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a50a0ddd2870cfaa6f8354b6c9bd05682">XV_HDMITX1_AUX_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(1*4))</td></tr>
<tr class="memdesc:a50a0ddd2870cfaa6f8354b6c9bd05682"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register * offset.  <a href="#a50a0ddd2870cfaa6f8354b6c9bd05682">More...</a><br/></td></tr>
<tr class="separator:a50a0ddd2870cfaa6f8354b6c9bd05682"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a97406fdf0b5b815f1a99e48f9f769ab9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(2*4))</td></tr>
<tr class="memdesc:a97406fdf0b5b815f1a99e48f9f769ab9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register Set * offset.  <a href="#a97406fdf0b5b815f1a99e48f9f769ab9">More...</a><br/></td></tr>
<tr class="separator:a97406fdf0b5b815f1a99e48f9f769ab9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a93a082440892ddad44f45085a507d526"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(3*4))</td></tr>
<tr class="memdesc:a93a082440892ddad44f45085a507d526"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register Clear * offset.  <a href="#a93a082440892ddad44f45085a507d526">More...</a><br/></td></tr>
<tr class="separator:a93a082440892ddad44f45085a507d526"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a14dcc9b57dc6ff4a5d43c9df86e54723"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a14dcc9b57dc6ff4a5d43c9df86e54723">XV_HDMITX1_AUX_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(4*4))</td></tr>
<tr class="memdesc:a14dcc9b57dc6ff4a5d43c9df86e54723"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Register * offset.  <a href="#a14dcc9b57dc6ff4a5d43c9df86e54723">More...</a><br/></td></tr>
<tr class="separator:a14dcc9b57dc6ff4a5d43c9df86e54723"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae77c642360ad975ab150de8a8c269d25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ae77c642360ad975ab150de8a8c269d25">XV_HDMITX1_AUX_DAT_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(5*4))</td></tr>
<tr class="memdesc:ae77c642360ad975ab150de8a8c269d25"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Data Register * offset.  <a href="#ae77c642360ad975ab150de8a8c269d25">More...</a><br/></td></tr>
<tr class="separator:ae77c642360ad975ab150de8a8c269d25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac512408565b031446c94da5f6a1d723d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ac512408565b031446c94da5f6a1d723d">XV_HDMITX1_AUX_VTEM_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(6*4))</td></tr>
<tr class="memdesc:ac512408565b031446c94da5f6a1d723d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX VTEM Register offset.  <a href="#ac512408565b031446c94da5f6a1d723d">More...</a><br/></td></tr>
<tr class="separator:ac512408565b031446c94da5f6a1d723d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a78c4e1ae6b49260a4f3337a7695d28f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a78c4e1ae6b49260a4f3337a7695d28f1">XV_HDMITX1_AUX_FSYNC_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(7*4))</td></tr>
<tr class="memdesc:a78c4e1ae6b49260a4f3337a7695d28f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC Register offset.  <a href="#a78c4e1ae6b49260a4f3337a7695d28f1">More...</a><br/></td></tr>
<tr class="separator:a78c4e1ae6b49260a4f3337a7695d28f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaa5bed5a9c240264e98a7821cd7d9945"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aaa5bed5a9c240264e98a7821cd7d9945">XV_HDMITX1_AUX_FSYNC_PRO_OF</a>&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(8*4))</td></tr>
<tr class="memdesc:aaa5bed5a9c240264e98a7821cd7d9945"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FYNC PRO Register offset.  <a href="#aaa5bed5a9c240264e98a7821cd7d9945">More...</a><br/></td></tr>
<tr class="separator:aaa5bed5a9c240264e98a7821cd7d9945"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af1aa16a7946897669f6883d9f0532cf2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#af1aa16a7946897669f6883d9f0532cf2">XV_HDMITX1_AUX_DYNHDR_PKT_OFFSET</a>&#160;&#160;&#160;(XV_HDMITX1_AUX_BASE + (9 * 4))</td></tr>
<tr class="memdesc:af1aa16a7946897669f6883d9f0532cf2"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Dynamic HDR Packet offset.  <a href="#af1aa16a7946897669f6883d9f0532cf2">More...</a><br/></td></tr>
<tr class="separator:af1aa16a7946897669f6883d9f0532cf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afb66a15f24bb7fe50bd7eefa2f92c733"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#afb66a15f24bb7fe50bd7eefa2f92c733">XV_HDMITX1_AUX_DYNHDR_ADDR_LSB_OFFSET</a>&#160;&#160;&#160;(XV_HDMITX1_AUX_BASE + (10 * 4))</td></tr>
<tr class="memdesc:afb66a15f24bb7fe50bd7eefa2f92c733"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Dynamic HDR Address LSB offset.  <a href="#afb66a15f24bb7fe50bd7eefa2f92c733">More...</a><br/></td></tr>
<tr class="separator:afb66a15f24bb7fe50bd7eefa2f92c733"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a40edecc0f4acd35d2e0a041a98f8051e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a40edecc0f4acd35d2e0a041a98f8051e">XV_HDMITX1_AUX_DYNHDR_ADDR_MSB_OFFSET</a>&#160;&#160;&#160;(XV_HDMITX1_AUX_BASE + (11 * 4))</td></tr>
<tr class="memdesc:a40edecc0f4acd35d2e0a041a98f8051e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Dynamic HDR Address MSB offset.  <a href="#a40edecc0f4acd35d2e0a041a98f8051e">More...</a><br/></td></tr>
<tr class="separator:a40edecc0f4acd35d2e0a041a98f8051e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add021f22d0ef7e0de595b74f105d4572"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#add021f22d0ef7e0de595b74f105d4572">XV_HDMITX1_AUX_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:add021f22d0ef7e0de595b74f105d4572"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Run mask.  <a href="#add021f22d0ef7e0de595b74f105d4572">More...</a><br/></td></tr>
<tr class="separator:add021f22d0ef7e0de595b74f105d4572"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f0047db6451a68373fa03364980db22"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a0f0047db6451a68373fa03364980db22">XV_HDMITX1_AUX_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a0f0047db6451a68373fa03364980db22"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Interrupt Enable mask.  <a href="#a0f0047db6451a68373fa03364980db22">More...</a><br/></td></tr>
<tr class="separator:a0f0047db6451a68373fa03364980db22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a09460db96023dedd0a3baf757e53447a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a09460db96023dedd0a3baf757e53447a">XV_HDMITX1_AUX_CTRL_VRR_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a09460db96023dedd0a3baf757e53447a"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control VRR En mask.  <a href="#a09460db96023dedd0a3baf757e53447a">More...</a><br/></td></tr>
<tr class="separator:a09460db96023dedd0a3baf757e53447a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acf287b290181336c53fc2c239b66a82f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#acf287b290181336c53fc2c239b66a82f">XV_HDMITX1_AUX_CTRL_FYSYNC_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:acf287b290181336c53fc2c239b66a82f"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control FSync En mask.  <a href="#acf287b290181336c53fc2c239b66a82f">More...</a><br/></td></tr>
<tr class="separator:acf287b290181336c53fc2c239b66a82f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa238147ea10632c793db777b956f97ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aa238147ea10632c793db777b956f97ea">XV_HDMITX1_AUX_CTRL_DYNHDR_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 4)</td></tr>
<tr class="memdesc:aa238147ea10632c793db777b956f97ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Enable Dynamic HDR mask.  <a href="#aa238147ea10632c793db777b956f97ea">More...</a><br/></td></tr>
<tr class="separator:aa238147ea10632c793db777b956f97ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a065623d68e18b9a4be22479637156a58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a065623d68e18b9a4be22479637156a58">XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 5)</td></tr>
<tr class="memdesc:a065623d68e18b9a4be22479637156a58"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Enable Graphic Overlay Flag mask.  <a href="#a065623d68e18b9a4be22479637156a58">More...</a><br/></td></tr>
<tr class="separator:a065623d68e18b9a4be22479637156a58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a11430497f5fdcaf795ac6aa779e45322"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a11430497f5fdcaf795ac6aa779e45322">XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_VAL_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 6)</td></tr>
<tr class="memdesc:a11430497f5fdcaf795ac6aa779e45322"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Graphic Overlay Flag value mask.  <a href="#a11430497f5fdcaf795ac6aa779e45322">More...</a><br/></td></tr>
<tr class="separator:a11430497f5fdcaf795ac6aa779e45322"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae12a08f10a443b8e49a07731cabc4ac7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ae12a08f10a443b8e49a07731cabc4ac7">XV_HDMITX1_AUX_CTRL_DYNHDR_FAPA_LOC_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 7)</td></tr>
<tr class="memdesc:ae12a08f10a443b8e49a07731cabc4ac7"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control FAPA Location value mask.  <a href="#ae12a08f10a443b8e49a07731cabc4ac7">More...</a><br/></td></tr>
<tr class="separator:ae12a08f10a443b8e49a07731cabc4ac7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac0c1dc603ec9771599bd82313b870bde"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ac0c1dc603ec9771599bd82313b870bde">XV_HDMITX1_AUX_CTRL_DSC_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:ac0c1dc603ec9771599bd82313b870bde"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control DSC En mask.  <a href="#ac0c1dc603ec9771599bd82313b870bde">More...</a><br/></td></tr>
<tr class="separator:ac0c1dc603ec9771599bd82313b870bde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3d2adfe31e66634e41b25537eb029883"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a3d2adfe31e66634e41b25537eb029883">XV_HDMITX1_AUX_CTRL_SYNC_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:a3d2adfe31e66634e41b25537eb029883"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control SYNC En mask.  <a href="#a3d2adfe31e66634e41b25537eb029883">More...</a><br/></td></tr>
<tr class="separator:a3d2adfe31e66634e41b25537eb029883"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa7fbb4e056d64a238f8170e398b20aed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aa7fbb4e056d64a238f8170e398b20aed">XV_HDMITX1_AUX_CTRL_DATASET_LEN_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:aa7fbb4e056d64a238f8170e398b20aed"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Data Set Length En mask.  <a href="#aa7fbb4e056d64a238f8170e398b20aed">More...</a><br/></td></tr>
<tr class="separator:aa7fbb4e056d64a238f8170e398b20aed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7add990341b3e99c486abdb4e730c5e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7add990341b3e99c486abdb4e730c5e2">XV_HDMITX1_AUX_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a7add990341b3e99c486abdb4e730c5e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Interrupt mask.  <a href="#a7add990341b3e99c486abdb4e730c5e2">More...</a><br/></td></tr>
<tr class="separator:a7add990341b3e99c486abdb4e730c5e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a64397a27f0e69610d66f0438c48f7ed4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a64397a27f0e69610d66f0438c48f7ed4">XV_HDMITX1_AUX_STA_FIFO_EMT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a64397a27f0e69610d66f0438c48f7ed4"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FIFO Empty mask.  <a href="#a64397a27f0e69610d66f0438c48f7ed4">More...</a><br/></td></tr>
<tr class="separator:a64397a27f0e69610d66f0438c48f7ed4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7bfb37aac0d6dd176a5d5be6e05697d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7bfb37aac0d6dd176a5d5be6e05697d9">XV_HDMITX1_AUX_STA_FIFO_FUL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a7bfb37aac0d6dd176a5d5be6e05697d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FIFO Full mask.  <a href="#a7bfb37aac0d6dd176a5d5be6e05697d9">More...</a><br/></td></tr>
<tr class="separator:a7bfb37aac0d6dd176a5d5be6e05697d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a778b10c4ff90127e6787100a6836a791"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a778b10c4ff90127e6787100a6836a791">XV_HDMITX1_AUX_STA_PKT_RDY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a778b10c4ff90127e6787100a6836a791"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FIFO Ready mask.  <a href="#a778b10c4ff90127e6787100a6836a791">More...</a><br/></td></tr>
<tr class="separator:a778b10c4ff90127e6787100a6836a791"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af34cd5972f20ed60467569002f116214"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#af34cd5972f20ed60467569002f116214">XV_HDMITX1_AUX_STA_FREE_PKTS_MASK</a>&#160;&#160;&#160;0x0F</td></tr>
<tr class="memdesc:af34cd5972f20ed60467569002f116214"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Free Packets mask.  <a href="#af34cd5972f20ed60467569002f116214">More...</a><br/></td></tr>
<tr class="separator:af34cd5972f20ed60467569002f116214"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a423f1fbdc32c8f7873cba83c18b36547"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a423f1fbdc32c8f7873cba83c18b36547">XV_HDMITX1_AUX_STA_FREE_PKTS_SHIFT</a>&#160;&#160;&#160;15</td></tr>
<tr class="memdesc:a423f1fbdc32c8f7873cba83c18b36547"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Free Packets shift.  <a href="#a423f1fbdc32c8f7873cba83c18b36547">More...</a><br/></td></tr>
<tr class="separator:a423f1fbdc32c8f7873cba83c18b36547"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a79b2893e2ea896e0def9b7b0685a5072"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a79b2893e2ea896e0def9b7b0685a5072">XV_HDMITX1_AUX_STA_DYNHDR_MTW_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 8)</td></tr>
<tr class="memdesc:a79b2893e2ea896e0def9b7b0685a5072"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Dynamic HDR MTW started.  <a href="#a79b2893e2ea896e0def9b7b0685a5072">More...</a><br/></td></tr>
<tr class="separator:a79b2893e2ea896e0def9b7b0685a5072"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a0133865be039e932ce2e7148d597f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a1a0133865be039e932ce2e7148d597f6">XV_HDMITX1_AUX_DYNHDR_RD_STS_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 9)</td></tr>
<tr class="memdesc:a1a0133865be039e932ce2e7148d597f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Dynamic HDR read response.  <a href="#a1a0133865be039e932ce2e7148d597f6">More...</a><br/></td></tr>
<tr class="separator:a1a0133865be039e932ce2e7148d597f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a823088b616d25a73ca25526d6bffd64c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a823088b616d25a73ca25526d6bffd64c">XV_HDMITX1_AUX_STA_DSC_PKT_WRRDY_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 10)</td></tr>
<tr class="memdesc:a823088b616d25a73ca25526d6bffd64c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status DSC Packet Write Ready.  <a href="#a823088b616d25a73ca25526d6bffd64c">More...</a><br/></td></tr>
<tr class="separator:a823088b616d25a73ca25526d6bffd64c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adbcd771bc70a5d6c60a250fa4fec98ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#adbcd771bc70a5d6c60a250fa4fec98ed">XV_HDMITX1_AUD_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(0*4))</td></tr>
<tr class="memdesc:adbcd771bc70a5d6c60a250fa4fec98ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Identification * Register offset.  <a href="#adbcd771bc70a5d6c60a250fa4fec98ed">More...</a><br/></td></tr>
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<tr class="memitem:a5c80837a1f240f83e131771e1180bf32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a5c80837a1f240f83e131771e1180bf32">XV_HDMITX1_AUD_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(1*4))</td></tr>
<tr class="memdesc:a5c80837a1f240f83e131771e1180bf32"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register * offset.  <a href="#a5c80837a1f240f83e131771e1180bf32">More...</a><br/></td></tr>
<tr class="separator:a5c80837a1f240f83e131771e1180bf32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac630a1dbb83be6d4e64757a3d09c2cc0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ac630a1dbb83be6d4e64757a3d09c2cc0">XV_HDMITX1_AUD_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(2*4))</td></tr>
<tr class="memdesc:ac630a1dbb83be6d4e64757a3d09c2cc0"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register Set * offset.  <a href="#ac630a1dbb83be6d4e64757a3d09c2cc0">More...</a><br/></td></tr>
<tr class="separator:ac630a1dbb83be6d4e64757a3d09c2cc0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a279874e2cee1de19fee34f5f25fe4198"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a279874e2cee1de19fee34f5f25fe4198">XV_HDMITX1_AUD_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(3*4))</td></tr>
<tr class="memdesc:a279874e2cee1de19fee34f5f25fe4198"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register Clear * offset.  <a href="#a279874e2cee1de19fee34f5f25fe4198">More...</a><br/></td></tr>
<tr class="separator:a279874e2cee1de19fee34f5f25fe4198"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad7fc0785dc15498cd0388a9dc9c2f849"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ad7fc0785dc15498cd0388a9dc9c2f849">XV_HDMITX1_AUD_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(4*4))</td></tr>
<tr class="memdesc:ad7fc0785dc15498cd0388a9dc9c2f849"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Register * offset.  <a href="#ad7fc0785dc15498cd0388a9dc9c2f849">More...</a><br/></td></tr>
<tr class="separator:ad7fc0785dc15498cd0388a9dc9c2f849"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a07578cb7628cd825336759685d553253"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a07578cb7628cd825336759685d553253">XV_HDMITX1_AUD_ACR_N_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(5*4))</td></tr>
<tr class="memdesc:a07578cb7628cd825336759685d553253"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Clock Regeneration CTS * Register offset.  <a href="#a07578cb7628cd825336759685d553253">More...</a><br/></td></tr>
<tr class="separator:a07578cb7628cd825336759685d553253"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adff5e5558c241deea3ea7bcd9c354a87"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#adff5e5558c241deea3ea7bcd9c354a87">XV_HDMITX1_AUD_ACR_CTS_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(6*4))</td></tr>
<tr class="memdesc:adff5e5558c241deea3ea7bcd9c354a87"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Clock Regeneration N * Register offset.  <a href="#adff5e5558c241deea3ea7bcd9c354a87">More...</a><br/></td></tr>
<tr class="separator:adff5e5558c241deea3ea7bcd9c354a87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0b6ca194e0811b7201545d206d1a49e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a0b6ca194e0811b7201545d206d1a49e3">XV_HDMITX1_AUD_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a0b6ca194e0811b7201545d206d1a49e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Run mask.  <a href="#a0b6ca194e0811b7201545d206d1a49e3">More...</a><br/></td></tr>
<tr class="separator:a0b6ca194e0811b7201545d206d1a49e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2afd77b61e076608260e0506604d95e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a2afd77b61e076608260e0506604d95e7">XV_HDMITX1_AUD_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a2afd77b61e076608260e0506604d95e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Interrupt Enable mask.  <a href="#a2afd77b61e076608260e0506604d95e7">More...</a><br/></td></tr>
<tr class="separator:a2afd77b61e076608260e0506604d95e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a29066f63afe9beeadac7a04ef1fecb3b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a29066f63afe9beeadac7a04ef1fecb3b">XV_HDMITX1_AUD_CTRL_CH_MASK</a>&#160;&#160;&#160;0x03</td></tr>
<tr class="memdesc:a29066f63afe9beeadac7a04ef1fecb3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control channels mask.  <a href="#a29066f63afe9beeadac7a04ef1fecb3b">More...</a><br/></td></tr>
<tr class="separator:a29066f63afe9beeadac7a04ef1fecb3b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a091a4a9dacc2d0fd8f881d5b6486f11e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a091a4a9dacc2d0fd8f881d5b6486f11e">XV_HDMITX1_AUD_CTRL_CH_SHIFT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:a091a4a9dacc2d0fd8f881d5b6486f11e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control channels mask.  <a href="#a091a4a9dacc2d0fd8f881d5b6486f11e">More...</a><br/></td></tr>
<tr class="separator:a091a4a9dacc2d0fd8f881d5b6486f11e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a07040ad23704877ed3f55d8f25456b95"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a07040ad23704877ed3f55d8f25456b95">XV_HDMITX1_3DAUD_CTRL_CH_MASK</a>&#160;&#160;&#160;0x07</td></tr>
<tr class="memdesc:a07040ad23704877ed3f55d8f25456b95"><td class="mdescLeft">&#160;</td><td class="mdescRight">3D AUD Control channels mask  <a href="#a07040ad23704877ed3f55d8f25456b95">More...</a><br/></td></tr>
<tr class="separator:a07040ad23704877ed3f55d8f25456b95"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a73acb585d91a8a036c65d832a7ff030d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a73acb585d91a8a036c65d832a7ff030d">XV_HDMITX1_3DAUD_CTRL_CH_SHIFT</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:a73acb585d91a8a036c65d832a7ff030d"><td class="mdescLeft">&#160;</td><td class="mdescRight">3D AUD Control channels mask  <a href="#a73acb585d91a8a036c65d832a7ff030d">More...</a><br/></td></tr>
<tr class="separator:a73acb585d91a8a036c65d832a7ff030d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a93c2f397d3ac840e116f0d2d9dd74262"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a93c2f397d3ac840e116f0d2d9dd74262">XV_HDMITX1_AUD_CTRL_AUDFMT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:a93c2f397d3ac840e116f0d2d9dd74262"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control AUD Format mask.  <a href="#a93c2f397d3ac840e116f0d2d9dd74262">More...</a><br/></td></tr>
<tr class="separator:a93c2f397d3ac840e116f0d2d9dd74262"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac103acef218d3189d2317c829c70e60e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ac103acef218d3189d2317c829c70e60e">XV_HDMITX1_AUD_CTRL_AUDFMT_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ac103acef218d3189d2317c829c70e60e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control AUD Format shift.  <a href="#ac103acef218d3189d2317c829c70e60e">More...</a><br/></td></tr>
<tr class="separator:ac103acef218d3189d2317c829c70e60e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52b9186ae2de6f7846338a83b0d7047f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a52b9186ae2de6f7846338a83b0d7047f">XV_HDMITX1_AUD_CTRL_3DAUDFMT_MASK</a>&#160;&#160;&#160;(0x3 &lt;&lt; 16)</td></tr>
<tr class="memdesc:a52b9186ae2de6f7846338a83b0d7047f"><td class="mdescLeft">&#160;</td><td class="mdescRight">3D AUD Control AUD Format mask  <a href="#a52b9186ae2de6f7846338a83b0d7047f">More...</a><br/></td></tr>
<tr class="separator:a52b9186ae2de6f7846338a83b0d7047f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2c371de5a34ac6143c1696f80581d23c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a2c371de5a34ac6143c1696f80581d23c">XV_HDMITX1_AUD_CTRL_3DAUDFMT_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a2c371de5a34ac6143c1696f80581d23c"><td class="mdescLeft">&#160;</td><td class="mdescRight">3DAUD Control AUD Format Format shift  <a href="#a2c371de5a34ac6143c1696f80581d23c">More...</a><br/></td></tr>
<tr class="separator:a2c371de5a34ac6143c1696f80581d23c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7098260b81b3a81f1325d55f3fc5e25a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7098260b81b3a81f1325d55f3fc5e25a">XV_HDMITX1_AUD_CTRL_3DAUDFMT_EN</a>&#160;&#160;&#160;(0x1 &lt;&lt; XV_HDMITX1_AUD_CTRL_3DAUDFMT_SHIFT)</td></tr>
<tr class="memdesc:a7098260b81b3a81f1325d55f3fc5e25a"><td class="mdescLeft">&#160;</td><td class="mdescRight">3DAUD en  <a href="#a7098260b81b3a81f1325d55f3fc5e25a">More...</a><br/></td></tr>
<tr class="separator:a7098260b81b3a81f1325d55f3fc5e25a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74d5b837a261a63b1e0e1bcf8c02f15e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a74d5b837a261a63b1e0e1bcf8c02f15e">XV_HDMITX1_AUD_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a74d5b837a261a63b1e0e1bcf8c02f15e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Interrupt mask.  <a href="#a74d5b837a261a63b1e0e1bcf8c02f15e">More...</a><br/></td></tr>
<tr class="separator:a74d5b837a261a63b1e0e1bcf8c02f15e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7b80b4e0c5104151bce62e9a679cd3cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7b80b4e0c5104151bce62e9a679cd3cb">XV_HDMITX1_AUD_ACR_N_MASK</a>&#160;&#160;&#160;0xFFFFF</td></tr>
<tr class="memdesc:a7b80b4e0c5104151bce62e9a679cd3cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD ACR N mask.  <a href="#a7b80b4e0c5104151bce62e9a679cd3cb">More...</a><br/></td></tr>
<tr class="separator:a7b80b4e0c5104151bce62e9a679cd3cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5a03022acaf171b71ed6d94b842997fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a5a03022acaf171b71ed6d94b842997fb">XV_HDMITX1_AUD_ACR_CTS_MASK</a>&#160;&#160;&#160;0xFFFFF</td></tr>
<tr class="memdesc:a5a03022acaf171b71ed6d94b842997fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD ACR CTS mask.  <a href="#a5a03022acaf171b71ed6d94b842997fb">More...</a><br/></td></tr>
<tr class="separator:a5a03022acaf171b71ed6d94b842997fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aee33576540fac84d5350f1a5d26b27bf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aee33576540fac84d5350f1a5d26b27bf">XV_HDMITX1_AUD_ACR_CTS_VLD_MASK</a>&#160;&#160;&#160;(1&lt;&lt;31)</td></tr>
<tr class="memdesc:aee33576540fac84d5350f1a5d26b27bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD ACR CTS Valid mask.  <a href="#aee33576540fac84d5350f1a5d26b27bf">More...</a><br/></td></tr>
<tr class="separator:aee33576540fac84d5350f1a5d26b27bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae0da2131cee32e9acfdbbc3a516af966"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ae0da2131cee32e9acfdbbc3a516af966">XV_HDMITX1_MASK_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(0*4))</td></tr>
<tr class="memdesc:ae0da2131cee32e9acfdbbc3a516af966"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Identification Register offset.  <a href="#ae0da2131cee32e9acfdbbc3a516af966">More...</a><br/></td></tr>
<tr class="separator:ae0da2131cee32e9acfdbbc3a516af966"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab6a37549bc9888ef902b62f9f0e30ef1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ab6a37549bc9888ef902b62f9f0e30ef1">XV_HDMITX1_MASK_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(1*4))</td></tr>
<tr class="memdesc:ab6a37549bc9888ef902b62f9f0e30ef1"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Control Register offset.  <a href="#ab6a37549bc9888ef902b62f9f0e30ef1">More...</a><br/></td></tr>
<tr class="separator:ab6a37549bc9888ef902b62f9f0e30ef1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac83138bb1465d39d0f80a53700c0b884"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ac83138bb1465d39d0f80a53700c0b884">XV_HDMITX1_MASK_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(2*4))</td></tr>
<tr class="memdesc:ac83138bb1465d39d0f80a53700c0b884"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Control Register Set offset.  <a href="#ac83138bb1465d39d0f80a53700c0b884">More...</a><br/></td></tr>
<tr class="separator:ac83138bb1465d39d0f80a53700c0b884"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a898ea3e6392a25115f070b6bd759e2c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a898ea3e6392a25115f070b6bd759e2c7">XV_HDMITX1_MASK_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(3*4))</td></tr>
<tr class="memdesc:a898ea3e6392a25115f070b6bd759e2c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Control Register Clear offset.  <a href="#a898ea3e6392a25115f070b6bd759e2c7">More...</a><br/></td></tr>
<tr class="separator:a898ea3e6392a25115f070b6bd759e2c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5bc7d731779d71bbcee75aed8ade8646"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a5bc7d731779d71bbcee75aed8ade8646">XV_HDMITX1_MASK_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(4*4))</td></tr>
<tr class="memdesc:a5bc7d731779d71bbcee75aed8ade8646"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Status Register offset.  <a href="#a5bc7d731779d71bbcee75aed8ade8646">More...</a><br/></td></tr>
<tr class="separator:a5bc7d731779d71bbcee75aed8ade8646"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a15730fa7eed0854af7219fdfecd974c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a15730fa7eed0854af7219fdfecd974c1">XV_HDMITX1_MASK_RED_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(5*4))</td></tr>
<tr class="memdesc:a15730fa7eed0854af7219fdfecd974c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Red Component Register offset.  <a href="#a15730fa7eed0854af7219fdfecd974c1">More...</a><br/></td></tr>
<tr class="separator:a15730fa7eed0854af7219fdfecd974c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1cac6ccd3a3706173ed032c701e14087"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a1cac6ccd3a3706173ed032c701e14087">XV_HDMITX1_MASK_GREEN_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(6*4))</td></tr>
<tr class="memdesc:a1cac6ccd3a3706173ed032c701e14087"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Green Component Register offset.  <a href="#a1cac6ccd3a3706173ed032c701e14087">More...</a><br/></td></tr>
<tr class="separator:a1cac6ccd3a3706173ed032c701e14087"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a20bd10d0de6ddcc5bd6b17b3c7121d65"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a20bd10d0de6ddcc5bd6b17b3c7121d65">XV_HDMITX1_MASK_BLUE_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(7*4))</td></tr>
<tr class="memdesc:a20bd10d0de6ddcc5bd6b17b3c7121d65"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Blue Component Register offset.  <a href="#a20bd10d0de6ddcc5bd6b17b3c7121d65">More...</a><br/></td></tr>
<tr class="separator:a20bd10d0de6ddcc5bd6b17b3c7121d65"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa76f75af182c527f0837a8e72e07a0ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aa76f75af182c527f0837a8e72e07a0ab">XV_HDMITX1_MASK_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:aa76f75af182c527f0837a8e72e07a0ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Control Run mask.  <a href="#aa76f75af182c527f0837a8e72e07a0ab">More...</a><br/></td></tr>
<tr class="separator:aa76f75af182c527f0837a8e72e07a0ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a59eb379430a75238522ae45d39bfb8e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a59eb379430a75238522ae45d39bfb8e7">XV_HDMITX1_MASK_CTRL_NOISE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a59eb379430a75238522ae45d39bfb8e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Control Noise.  <a href="#a59eb379430a75238522ae45d39bfb8e7">More...</a><br/></td></tr>
<tr class="separator:a59eb379430a75238522ae45d39bfb8e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeec6c916c6052f91599bb74debafaee1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aeec6c916c6052f91599bb74debafaee1">XV_HDMITX1_FRL_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(0*4))</td></tr>
<tr class="memdesc:aeec6c916c6052f91599bb74debafaee1"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Identification Register offset.  <a href="#aeec6c916c6052f91599bb74debafaee1">More...</a><br/></td></tr>
<tr class="separator:aeec6c916c6052f91599bb74debafaee1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc06f99f814e758f194f5afab57fd7e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#abc06f99f814e758f194f5afab57fd7e1">XV_HDMITX1_FRL_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(1*4))</td></tr>
<tr class="memdesc:abc06f99f814e758f194f5afab57fd7e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Register offset.  <a href="#abc06f99f814e758f194f5afab57fd7e1">More...</a><br/></td></tr>
<tr class="separator:abc06f99f814e758f194f5afab57fd7e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae76270b448224670d8cd9615dbac2091"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ae76270b448224670d8cd9615dbac2091">XV_HDMITX1_FRL_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(2*4))</td></tr>
<tr class="memdesc:ae76270b448224670d8cd9615dbac2091"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Register Set offset.  <a href="#ae76270b448224670d8cd9615dbac2091">More...</a><br/></td></tr>
<tr class="separator:ae76270b448224670d8cd9615dbac2091"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa5da06390a2ac2dc17a7581c3cc7f81a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aa5da06390a2ac2dc17a7581c3cc7f81a">XV_HDMITX1_FRL_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(3*4))</td></tr>
<tr class="memdesc:aa5da06390a2ac2dc17a7581c3cc7f81a"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Register Clear offset.  <a href="#aa5da06390a2ac2dc17a7581c3cc7f81a">More...</a><br/></td></tr>
<tr class="separator:aa5da06390a2ac2dc17a7581c3cc7f81a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af69097b14c333e4e03d8934c68e5666a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#af69097b14c333e4e03d8934c68e5666a">XV_HDMITX1_FRL_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(4*4))</td></tr>
<tr class="memdesc:af69097b14c333e4e03d8934c68e5666a"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Register offset.  <a href="#af69097b14c333e4e03d8934c68e5666a">More...</a><br/></td></tr>
<tr class="separator:af69097b14c333e4e03d8934c68e5666a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1af817a6e8f37b0a75cf466dd7b2e5c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a1af817a6e8f37b0a75cf466dd7b2e5c2">XV_HDMITX1_FRL_TMR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(5*4))</td></tr>
<tr class="memdesc:a1af817a6e8f37b0a75cf466dd7b2e5c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Timer Register offset.  <a href="#a1af817a6e8f37b0a75cf466dd7b2e5c2">More...</a><br/></td></tr>
<tr class="separator:a1af817a6e8f37b0a75cf466dd7b2e5c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abcfb2ad0c96c0240bd2211dba81810d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#abcfb2ad0c96c0240bd2211dba81810d0">XV_HDMITX1_FRL_LNK_CLK_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(6*4))</td></tr>
<tr class="memdesc:abcfb2ad0c96c0240bd2211dba81810d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Link Clock Register offset.  <a href="#abcfb2ad0c96c0240bd2211dba81810d0">More...</a><br/></td></tr>
<tr class="separator:abcfb2ad0c96c0240bd2211dba81810d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae77246dd4776e8a41f7b92c093c4e1a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ae77246dd4776e8a41f7b92c093c4e1a0">XV_HDMITX1_FRL_VID_CLK_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(7*4))</td></tr>
<tr class="memdesc:ae77246dd4776e8a41f7b92c093c4e1a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Video Clock Register offset.  <a href="#ae77246dd4776e8a41f7b92c093c4e1a0">More...</a><br/></td></tr>
<tr class="separator:ae77246dd4776e8a41f7b92c093c4e1a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a46be7703d3c31e502bc366ec590b02b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a46be7703d3c31e502bc366ec590b02b3">XV_HDMITX1_FRL_VP_FIFO_THRD_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(8*4))</td></tr>
<tr class="memdesc:a46be7703d3c31e502bc366ec590b02b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Video Packetizer FIFO Threshold Register offset.  <a href="#a46be7703d3c31e502bc366ec590b02b3">More...</a><br/></td></tr>
<tr class="separator:a46be7703d3c31e502bc366ec590b02b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a97c6f090d853e1c36621b67c0b78472e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a97c6f090d853e1c36621b67c0b78472e">XV_HDMITX1_FRL_DISP_ERR_INJ_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(9*4))</td></tr>
<tr class="memdesc:a97c6f090d853e1c36621b67c0b78472e"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Disparity Error Injector Register offset.  <a href="#a97c6f090d853e1c36621b67c0b78472e">More...</a><br/></td></tr>
<tr class="separator:a97c6f090d853e1c36621b67c0b78472e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a91a37eb1ef5f54705a9643b9ff7c8797"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a91a37eb1ef5f54705a9643b9ff7c8797">XV_HDMITX1_FRL_FEC_ERR_INJ_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(10*4))</td></tr>
<tr class="memdesc:a91a37eb1ef5f54705a9643b9ff7c8797"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL FEC Error Injector Register offset.  <a href="#a91a37eb1ef5f54705a9643b9ff7c8797">More...</a><br/></td></tr>
<tr class="separator:a91a37eb1ef5f54705a9643b9ff7c8797"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af0adeaa6e6dbbf9da1aa465dbe5801c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#af0adeaa6e6dbbf9da1aa465dbe5801c8">XV_HDMITX1_FRL_CTRL_RSTN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:af0adeaa6e6dbbf9da1aa465dbe5801c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Resetn mask.  <a href="#af0adeaa6e6dbbf9da1aa465dbe5801c8">More...</a><br/></td></tr>
<tr class="separator:af0adeaa6e6dbbf9da1aa465dbe5801c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a143c3655dacc300a41dac7cbe34c4ed7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a143c3655dacc300a41dac7cbe34c4ed7">XV_HDMITX1_FRL_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a143c3655dacc300a41dac7cbe34c4ed7"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Interrupt Enable mask.  <a href="#a143c3655dacc300a41dac7cbe34c4ed7">More...</a><br/></td></tr>
<tr class="separator:a143c3655dacc300a41dac7cbe34c4ed7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af14a628baf787a604f23d2114b5ef16a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#af14a628baf787a604f23d2114b5ef16a">XV_HDMITX1_FRL_CTRL_OP_MODE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:af14a628baf787a604f23d2114b5ef16a"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Operation Mode mask.  <a href="#af14a628baf787a604f23d2114b5ef16a">More...</a><br/></td></tr>
<tr class="separator:af14a628baf787a604f23d2114b5ef16a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5fe062b0a3114ac13ab10e99fd02dcd3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a5fe062b0a3114ac13ab10e99fd02dcd3">XV_HDMITX1_FRL_CTRL_LN_OP_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a5fe062b0a3114ac13ab10e99fd02dcd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane Operation mask.  <a href="#a5fe062b0a3114ac13ab10e99fd02dcd3">More...</a><br/></td></tr>
<tr class="separator:a5fe062b0a3114ac13ab10e99fd02dcd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6e9c4eff210d0862e3e7ca94bf7fa0e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a6e9c4eff210d0862e3e7ca94bf7fa0e6">XV_HDMITX1_FRL_CTRL_EXEC_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:a6e9c4eff210d0862e3e7ca94bf7fa0e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL execute mask.  <a href="#a6e9c4eff210d0862e3e7ca94bf7fa0e6">More...</a><br/></td></tr>
<tr class="separator:a6e9c4eff210d0862e3e7ca94bf7fa0e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a796e498d647fa273f085bc9a561b32b0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a796e498d647fa273f085bc9a561b32b0">XV_HDMITX1_FRL_CTRL_TST_RC_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:a796e498d647fa273f085bc9a561b32b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL RC Compress mask.  <a href="#a796e498d647fa273f085bc9a561b32b0">More...</a><br/></td></tr>
<tr class="separator:a796e498d647fa273f085bc9a561b32b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4106f7902fe789c40042b05956e9ee39"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a4106f7902fe789c40042b05956e9ee39">XV_HDMITX1_FRL_ACT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:a4106f7902fe789c40042b05956e9ee39"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Active mask.  <a href="#a4106f7902fe789c40042b05956e9ee39">More...</a><br/></td></tr>
<tr class="separator:a4106f7902fe789c40042b05956e9ee39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7505796b81e52d346f14abb3b1a24bfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7505796b81e52d346f14abb3b1a24bfa">XV_HDMITX1_FRL_LTP0_REQ_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a7505796b81e52d346f14abb3b1a24bfa"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 0 LTP mask.  <a href="#a7505796b81e52d346f14abb3b1a24bfa">More...</a><br/></td></tr>
<tr class="separator:a7505796b81e52d346f14abb3b1a24bfa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a53c5fc702ac87b8400ece0a29d50177b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a53c5fc702ac87b8400ece0a29d50177b">XV_HDMITX1_FRL_LTP0_REQ_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a53c5fc702ac87b8400ece0a29d50177b"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 0 LTP shift.  <a href="#a53c5fc702ac87b8400ece0a29d50177b">More...</a><br/></td></tr>
<tr class="separator:a53c5fc702ac87b8400ece0a29d50177b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa0d9f55a85e21c40e6ffd24e8435a9e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aa0d9f55a85e21c40e6ffd24e8435a9e6">XV_HDMITX1_FRL_LTP1_REQ_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:aa0d9f55a85e21c40e6ffd24e8435a9e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 1 LTP mask.  <a href="#aa0d9f55a85e21c40e6ffd24e8435a9e6">More...</a><br/></td></tr>
<tr class="separator:aa0d9f55a85e21c40e6ffd24e8435a9e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a232c20ed50d25e04f96b918341d9855d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a232c20ed50d25e04f96b918341d9855d">XV_HDMITX1_FRL_LTP1_REQ_SHIFT</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:a232c20ed50d25e04f96b918341d9855d"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 1 LTP shift.  <a href="#a232c20ed50d25e04f96b918341d9855d">More...</a><br/></td></tr>
<tr class="separator:a232c20ed50d25e04f96b918341d9855d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a155553393f06b1a723b3c31398279c1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a155553393f06b1a723b3c31398279c1b">XV_HDMITX1_FRL_LTP2_REQ_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a155553393f06b1a723b3c31398279c1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 2 LTP mask.  <a href="#a155553393f06b1a723b3c31398279c1b">More...</a><br/></td></tr>
<tr class="separator:a155553393f06b1a723b3c31398279c1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a97e4f75036407536b66c397d45f641af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a97e4f75036407536b66c397d45f641af">XV_HDMITX1_FRL_LTP2_REQ_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a97e4f75036407536b66c397d45f641af"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 2 LTP shift.  <a href="#a97e4f75036407536b66c397d45f641af">More...</a><br/></td></tr>
<tr class="separator:a97e4f75036407536b66c397d45f641af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaa4c8e59d103740cb1916f20154e2860"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aaa4c8e59d103740cb1916f20154e2860">XV_HDMITX1_FRL_LTP3_REQ_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:aaa4c8e59d103740cb1916f20154e2860"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 3 LTP mask.  <a href="#aaa4c8e59d103740cb1916f20154e2860">More...</a><br/></td></tr>
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<tr class="memitem:a8809fb1d8b55f999acb54a84945598d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a8809fb1d8b55f999acb54a84945598d2">XV_HDMITX1_FRL_LTP3_REQ_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:a8809fb1d8b55f999acb54a84945598d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 3 LTP shift.  <a href="#a8809fb1d8b55f999acb54a84945598d2">More...</a><br/></td></tr>
<tr class="separator:a8809fb1d8b55f999acb54a84945598d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab43b8614d7ac425f46252b52f4934fe5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ab43b8614d7ac425f46252b52f4934fe5">XV_HDMITX1_FRL_VCKE_EXT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;24)</td></tr>
<tr class="memdesc:ab43b8614d7ac425f46252b52f4934fe5"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Lane 3 LTP mask.  <a href="#ab43b8614d7ac425f46252b52f4934fe5">More...</a><br/></td></tr>
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<tr class="memitem:ad6246682008ba157f08ac24f80294eed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ad6246682008ba157f08ac24f80294eed">XV_HDMITX1_FRL_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:ad6246682008ba157f08ac24f80294eed"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Interrupt mask.  <a href="#ad6246682008ba157f08ac24f80294eed">More...</a><br/></td></tr>
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<tr class="memitem:ad4f33b6056280050b315f32f9e1dd9c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ad4f33b6056280050b315f32f9e1dd9c0">XV_HDMITX1_FRL_STA_TMR_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ad4f33b6056280050b315f32f9e1dd9c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Timer Event mask.  <a href="#ad4f33b6056280050b315f32f9e1dd9c0">More...</a><br/></td></tr>
<tr class="separator:ad4f33b6056280050b315f32f9e1dd9c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a493218b41f2d420b0c003ba1bcde8dd0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a493218b41f2d420b0c003ba1bcde8dd0">XV_HDMITX1_FRL_STA_TMR_ZERO_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a493218b41f2d420b0c003ba1bcde8dd0"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Timer Zero mask.  <a href="#a493218b41f2d420b0c003ba1bcde8dd0">More...</a><br/></td></tr>
<tr class="separator:a493218b41f2d420b0c003ba1bcde8dd0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab4f48aa33f3800c755542f68a044ee1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ab4f48aa33f3800c755542f68a044ee1b">XV_HDMITX1_FRL_STA_FRL_RST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:ab4f48aa33f3800c755542f68a044ee1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status FRL Reset mask.  <a href="#ab4f48aa33f3800c755542f68a044ee1b">More...</a><br/></td></tr>
<tr class="separator:ab4f48aa33f3800c755542f68a044ee1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4fd5e5b43cf47643292c1b384a10defa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a4fd5e5b43cf47643292c1b384a10defa">XV_HDMITX1_FRL_STA_TRIB_RST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:a4fd5e5b43cf47643292c1b384a10defa"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status TRIB Reset mask.  <a href="#a4fd5e5b43cf47643292c1b384a10defa">More...</a><br/></td></tr>
<tr class="separator:a4fd5e5b43cf47643292c1b384a10defa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab380ac5aacd7ffc41be4c522f4a86b76"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#ab380ac5aacd7ffc41be4c522f4a86b76">XV_HDMITX1_FRL_STA_LNK_CLK_OOS_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:ab380ac5aacd7ffc41be4c522f4a86b76"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Link Clock OOS mask.  <a href="#ab380ac5aacd7ffc41be4c522f4a86b76">More...</a><br/></td></tr>
<tr class="separator:ab380ac5aacd7ffc41be4c522f4a86b76"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a67df2123a9cead20b89e2898d3966f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a1a67df2123a9cead20b89e2898d3966f">XV_HDMITX1_FRL_STA_VID_CLK_OOS_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:a1a67df2123a9cead20b89e2898d3966f"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Video Clock OOS mask.  <a href="#a1a67df2123a9cead20b89e2898d3966f">More...</a><br/></td></tr>
<tr class="separator:a1a67df2123a9cead20b89e2898d3966f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa3e6dcf348fd94a3c350bf239eefee9f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aa3e6dcf348fd94a3c350bf239eefee9f">XV_HDMITX1_FRL_STA_GB_EP_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:aa3e6dcf348fd94a3c350bf239eefee9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Gearbox EP mask.  <a href="#aa3e6dcf348fd94a3c350bf239eefee9f">More...</a><br/></td></tr>
<tr class="separator:aa3e6dcf348fd94a3c350bf239eefee9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aefff5c96f7b61d619e959fb994a331e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#aefff5c96f7b61d619e959fb994a331e6">XV_HDMITX1_FRL_STA_GB_SYNC_ERR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:aefff5c96f7b61d619e959fb994a331e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Gearbox Sync Error mask.  <a href="#aefff5c96f7b61d619e959fb994a331e6">More...</a><br/></td></tr>
<tr class="separator:aefff5c96f7b61d619e959fb994a331e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a9af7e806864a693da679c6ccffb125"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a7a9af7e806864a693da679c6ccffb125">XV_HDMITX1_FRL_LNK_CLK_MASK</a>&#160;&#160;&#160;0xFFFFF</td></tr>
<tr class="memdesc:a7a9af7e806864a693da679c6ccffb125"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Link Clock mask.  <a href="#a7a9af7e806864a693da679c6ccffb125">More...</a><br/></td></tr>
<tr class="separator:a7a9af7e806864a693da679c6ccffb125"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a31e6bd2a3c47baf19720a962373e49a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a31e6bd2a3c47baf19720a962373e49a9">XV_HDMITX1_FRL_VID_CLK_MASK</a>&#160;&#160;&#160;0xFFFFF</td></tr>
<tr class="memdesc:a31e6bd2a3c47baf19720a962373e49a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Video Clock mask.  <a href="#a31e6bd2a3c47baf19720a962373e49a9">More...</a><br/></td></tr>
<tr class="separator:a31e6bd2a3c47baf19720a962373e49a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a46be7703d3c31e502bc366ec590b02b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a46be7703d3c31e502bc366ec590b02b3">XV_HDMITX1_FRL_VP_FIFO_THRD_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(8*4))</td></tr>
<tr class="memdesc:a46be7703d3c31e502bc366ec590b02b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Video Packetizer FIFO Threshold Register offset.  <a href="#a46be7703d3c31e502bc366ec590b02b3">More...</a><br/></td></tr>
<tr class="separator:a46be7703d3c31e502bc366ec590b02b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a97c6f090d853e1c36621b67c0b78472e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a97c6f090d853e1c36621b67c0b78472e">XV_HDMITX1_FRL_DISP_ERR_INJ_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(9*4))</td></tr>
<tr class="memdesc:a97c6f090d853e1c36621b67c0b78472e"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Disparity Error Injector Register offset.  <a href="#a97c6f090d853e1c36621b67c0b78472e">More...</a><br/></td></tr>
<tr class="separator:a97c6f090d853e1c36621b67c0b78472e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a91a37eb1ef5f54705a9643b9ff7c8797"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a91a37eb1ef5f54705a9643b9ff7c8797">XV_HDMITX1_FRL_FEC_ERR_INJ_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(10*4))</td></tr>
<tr class="memdesc:a91a37eb1ef5f54705a9643b9ff7c8797"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL FEC Error Injector Register offset.  <a href="#a91a37eb1ef5f54705a9643b9ff7c8797">More...</a><br/></td></tr>
<tr class="separator:a91a37eb1ef5f54705a9643b9ff7c8797"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52b7d366cc179f1aa90b20ae9ed5a6de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a52b7d366cc179f1aa90b20ae9ed5a6de">XV_HDMITX1_SHIFT_16</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a52b7d366cc179f1aa90b20ae9ed5a6de"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 shift value  <a href="#a52b7d366cc179f1aa90b20ae9ed5a6de">More...</a><br/></td></tr>
<tr class="separator:a52b7d366cc179f1aa90b20ae9ed5a6de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a02751a20bad34eb921ded41ecd6449bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a02751a20bad34eb921ded41ecd6449bd">XV_HDMITX1_MASK_16</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a02751a20bad34eb921ded41ecd6449bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 bit mask value  <a href="#a02751a20bad34eb921ded41ecd6449bd">More...</a><br/></td></tr>
<tr class="separator:a02751a20bad34eb921ded41ecd6449bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a85275d4df3edf2c08d38d544b5928c95"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a85275d4df3edf2c08d38d544b5928c95">XV_HDMITX1_PIO_ID</a>&#160;&#160;&#160;0x2200</td></tr>
<tr class="memdesc:a85275d4df3edf2c08d38d544b5928c95"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX's PIO ID.  <a href="#a85275d4df3edf2c08d38d544b5928c95">More...</a><br/></td></tr>
<tr class="separator:a85275d4df3edf2c08d38d544b5928c95"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a509f93707c8ca85278312981c1db7974"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a509f93707c8ca85278312981c1db7974">XV_HdmiTx1_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:a509f93707c8ca85278312981c1db7974"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="#a509f93707c8ca85278312981c1db7974">More...</a><br/></td></tr>
<tr class="separator:a509f93707c8ca85278312981c1db7974"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adc4c9715f4a62bd5213ab32e59feb4de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#adc4c9715f4a62bd5213ab32e59feb4de">XV_HdmiTx1_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:adc4c9715f4a62bd5213ab32e59feb4de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="#adc4c9715f4a62bd5213ab32e59feb4de">More...</a><br/></td></tr>
<tr class="separator:adc4c9715f4a62bd5213ab32e59feb4de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a374eee1fb3e859285b0e6deeb5cd3b7b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="xv__hdmitx1__hw_8h.html#a509f93707c8ca85278312981c1db7974">XV_HdmiTx1_In32</a>((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:a374eee1fb3e859285b0e6deeb5cd3b7b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a HDMI TX register.  <a href="#a374eee1fb3e859285b0e6deeb5cd3b7b">More...</a><br/></td></tr>
<tr class="separator:a374eee1fb3e859285b0e6deeb5cd3b7b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af4ba16c8e4e0505aa1e7ea79d06eb2d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="xv__hdmitx1__hw_8h.html#adc4c9715f4a62bd5213ab32e59feb4de">XV_HdmiTx1_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:af4ba16c8e4e0505aa1e7ea79d06eb2d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a HDMI TX register.  <a href="#af4ba16c8e4e0505aa1e7ea79d06eb2d4">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a07040ad23704877ed3f55d8f25456b95"></a>
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          <td class="memname">#define XV_HDMITX1_3DAUD_CTRL_CH_MASK&#160;&#160;&#160;0x07</td>
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<p>3D AUD Control channels mask </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels()</a>.</p>

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          <td class="memname">#define XV_HDMITX1_3DAUD_CTRL_CH_SHIFT&#160;&#160;&#160;18</td>
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<p>3D AUD Control channels mask </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels()</a>.</p>

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<a class="anchor" id="afb2c02dfd40e7248cb5137d1fda16451"></a>
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          <td class="memname">#define XV_HDMITX1_ANLZ_HBP_HS_HPB_SZ_MASK&#160;&#160;&#160;0xFFFF</td>
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<p>Analyzer hbp size mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

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<a class="anchor" id="a0b0c1fc1bd8023ff5443e48be1a37d52"></a>
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          <td class="memname">#define XV_HDMITX1_ANLZ_HBP_HS_HPB_SZ_SHIFT&#160;&#160;&#160;16</td>
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<p>Analyzer hbp size shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

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          <td class="memname">#define XV_HDMITX1_ANLZ_HBP_HS_HS_SZ_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Analyzer hsync size mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a3dc6081400d3494ea259bb6edd5c1522"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_ANLZ_HBP_HS_HS_SZ_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Analyzer hsync size shift. </p>

</div>
</div>
<a class="anchor" id="a1e0129ded92751eb5637c0d3a3af7ec7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_ANLZ_HBP_HS_OFFSET&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Analyzer HPB HS Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ab5ee2d3c0b53adc5e1baabe4bc0d8471"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_ANLZ_LN_ACT_ACT_SZ_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Analyzer analyzer act size mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a847e52c070dcb42614e10c47e6ca437b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_ANLZ_LN_ACT_ACT_SZ_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Analyzer analyzer act size shift. </p>

</div>
</div>
<a class="anchor" id="a553fc17abc52bfc2212f49243b910963"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_ANLZ_LN_ACT_LN_SZ_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Analyzer analyzer line act mask. </p>
<p>PIO (Parallel Interface) peripheral register offsets The PIO is the first peripheral on the local bus </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="aecc45e839afee440ecd5c614a0f6c379"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_ANLZ_LN_ACT_LN_SZ_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Analyzer analyzer line act shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ad97a50cec14720080dc2ff6e5fd41809"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_ANLZ_LN_ACT_OFFSET&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Analyzer LN ACT Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a5a03022acaf171b71ed6d94b842997fb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_ACR_CTS_MASK&#160;&#160;&#160;0xFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD ACR CTS mask. </p>

</div>
</div>
<a class="anchor" id="adff5e5558c241deea3ea7bcd9c354a87"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_ACR_CTS_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Clock Regeneration N * Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a937b182eae5d5d5eefe0e7cbc0e833c7">XV_HdmiTxSs1_GetAudioCtsVal()</a>.</p>

</div>
</div>
<a class="anchor" id="aee33576540fac84d5350f1a5d26b27bf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_ACR_CTS_VLD_MASK&#160;&#160;&#160;(1&lt;&lt;31)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD ACR CTS Valid mask. </p>

</div>
</div>
<a class="anchor" id="a7b80b4e0c5104151bce62e9a679cd3cb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_ACR_N_MASK&#160;&#160;&#160;0xFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD ACR N mask. </p>

</div>
</div>
<a class="anchor" id="a07578cb7628cd825336759685d553253"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_ACR_N_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Clock Regeneration CTS * Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ad22b60a3d798ee469dcc71a04100843d">XV_HdmiTx1_FRLACRStart()</a>, <a class="el" href="xv__hdmitx1_8h.html#a7f1498e69d193cbd626999414e863558">XV_HdmiTx1_TMDSACRStart()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a58b5302d9843f58fcf1336d2a0ab9bcd">XV_HdmiTxSs1_GetAudioNVal()</a>.</p>

</div>
</div>
<a class="anchor" id="a7098260b81b3a81f1325d55f3fc5e25a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_3DAUDFMT_EN&#160;&#160;&#160;(0x1 &lt;&lt; XV_HDMITX1_AUD_CTRL_3DAUDFMT_SHIFT)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>3DAUD en </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a23a20e6c1144064686e03fd0650ec46f">XV_HdmiTx1_SetAudioFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="a52b9186ae2de6f7846338a83b0d7047f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_3DAUDFMT_MASK&#160;&#160;&#160;(0x3 &lt;&lt; 16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>3D AUD Control AUD Format mask </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae2022f3a37591ca01f2028e0e938e331">XV_HdmiTx1_GetAudioFormat()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a23a20e6c1144064686e03fd0650ec46f">XV_HdmiTx1_SetAudioFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="a2c371de5a34ac6143c1696f80581d23c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_3DAUDFMT_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>3DAUD Control AUD Format Format shift </p>

</div>
</div>
<a class="anchor" id="a93c2f397d3ac840e116f0d2d9dd74262"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_AUDFMT_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control AUD Format mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae2022f3a37591ca01f2028e0e938e331">XV_HdmiTx1_GetAudioFormat()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a23a20e6c1144064686e03fd0650ec46f">XV_HdmiTx1_SetAudioFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="ac103acef218d3189d2317c829c70e60e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_AUDFMT_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control AUD Format shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae2022f3a37591ca01f2028e0e938e331">XV_HdmiTx1_GetAudioFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="a29066f63afe9beeadac7a04ef1fecb3b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_CH_MASK&#160;&#160;&#160;0x03</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control channels mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels()</a>.</p>

</div>
</div>
<a class="anchor" id="a091a4a9dacc2d0fd8f881d5b6486f11e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_CH_SHIFT&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control channels mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels()</a>.</p>

</div>
</div>
<a class="anchor" id="a279874e2cee1de19fee34f5f25fe4198"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register Clear * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, <a class="el" href="xv__hdmitx1_8h.html#ad22b60a3d798ee469dcc71a04100843d">XV_HdmiTx1_FRLACRStart()</a>, <a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels()</a>, <a class="el" href="xv__hdmitx1_8h.html#a23a20e6c1144064686e03fd0650ec46f">XV_HdmiTx1_SetAudioFormat()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a7f1498e69d193cbd626999414e863558">XV_HdmiTx1_TMDSACRStart()</a>.</p>

</div>
</div>
<a class="anchor" id="a2afd77b61e076608260e0506604d95e7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a5c80837a1f240f83e131771e1180bf32"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae2022f3a37591ca01f2028e0e938e331">XV_HdmiTx1_GetAudioFormat()</a>, <a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a23a20e6c1144064686e03fd0650ec46f">XV_HdmiTx1_SetAudioFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="a0b6ca194e0811b7201545d206d1a49e3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Run mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae842f2e11b05dbc07382f202bffbf7ea">XV_HdmiTx1_AudioEnable()</a>, <a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a23a20e6c1144064686e03fd0650ec46f">XV_HdmiTx1_SetAudioFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="ac630a1dbb83be6d4e64757a3d09c2cc0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register Set * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae842f2e11b05dbc07382f202bffbf7ea">XV_HdmiTx1_AudioEnable()</a>, <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, <a class="el" href="xv__hdmitx1_8h.html#ad22b60a3d798ee469dcc71a04100843d">XV_HdmiTx1_FRLACRStart()</a>, <a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels()</a>, <a class="el" href="xv__hdmitx1_8h.html#a23a20e6c1144064686e03fd0650ec46f">XV_HdmiTx1_SetAudioFormat()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a7f1498e69d193cbd626999414e863558">XV_HdmiTx1_TMDSACRStart()</a>.</p>

</div>
</div>
<a class="anchor" id="adbcd771bc70a5d6c60a250fa4fec98ed"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Identification * Register offset. </p>

</div>
</div>
<a class="anchor" id="a74d5b837a261a63b1e0e1bcf8c02f15e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Interrupt mask. </p>

</div>
</div>
<a class="anchor" id="ad7fc0785dc15498cd0388a9dc9c2f849"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUD_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUD_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Register * offset. </p>

</div>
</div>
<a class="anchor" id="a93a082440892ddad44f45085a507d526"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register Clear * offset. </p>

</div>
</div>
<a class="anchor" id="aa7fbb4e056d64a238f8170e398b20aed"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_DATASET_LEN_EN_MASK&#160;&#160;&#160;(1&lt;&lt;10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Data Set Length En mask. </p>

</div>
</div>
<a class="anchor" id="ac0c1dc603ec9771599bd82313b870bde"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_DSC_EN_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control DSC En mask. </p>

</div>
</div>
<a class="anchor" id="aa238147ea10632c793db777b956f97ea"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_DYNHDR_EN_MASK&#160;&#160;&#160;(1 &lt;&lt; 4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Enable Dynamic HDR mask. </p>

</div>
</div>
<a class="anchor" id="ae12a08f10a443b8e49a07731cabc4ac7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_DYNHDR_FAPA_LOC_MASK&#160;&#160;&#160;(1 &lt;&lt; 7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control FAPA Location value mask. </p>

</div>
</div>
<a class="anchor" id="a065623d68e18b9a4be22479637156a58"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_EN_MASK&#160;&#160;&#160;(1 &lt;&lt; 5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Enable Graphic Overlay Flag mask. </p>

</div>
</div>
<a class="anchor" id="a11430497f5fdcaf795ac6aa779e45322"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_VAL_MASK&#160;&#160;&#160;(1 &lt;&lt; 6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Graphic Overlay Flag value mask. </p>

</div>
</div>
<a class="anchor" id="acf287b290181336c53fc2c239b66a82f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_FYSYNC_EN_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control FSync En mask. </p>

</div>
</div>
<a class="anchor" id="a0f0047db6451a68373fa03364980db22"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a50a0ddd2870cfaa6f8354b6c9bd05682"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register * offset. </p>

</div>
</div>
<a class="anchor" id="add021f22d0ef7e0de595b74f105d4572"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Run mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a1b7d74b3288271064644bda7857a1c8b">XV_HdmiTx1_AuxEnable()</a>.</p>

</div>
</div>
<a class="anchor" id="a97406fdf0b5b815f1a99e48f9f769ab9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register Set * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a1b7d74b3288271064644bda7857a1c8b">XV_HdmiTx1_AuxEnable()</a>.</p>

</div>
</div>
<a class="anchor" id="a3d2adfe31e66634e41b25537eb029883"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_SYNC_EN_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control SYNC En mask. </p>

</div>
</div>
<a class="anchor" id="a09460db96023dedd0a3baf757e53447a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_CTRL_VRR_EN_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control VRR En mask. </p>

</div>
</div>
<a class="anchor" id="ae77c642360ad975ab150de8a8c269d25"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_DAT_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Data Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a49560390a20d63cec3fd7c79c2f44a76">XV_HdmiTx1_AuxSend()</a>.</p>

</div>
</div>
<a class="anchor" id="afb66a15f24bb7fe50bd7eefa2f92c733"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_DYNHDR_ADDR_LSB_OFFSET&#160;&#160;&#160;(XV_HDMITX1_AUX_BASE + (10 * 4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Dynamic HDR Address LSB offset. </p>

</div>
</div>
<a class="anchor" id="a40edecc0f4acd35d2e0a041a98f8051e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_DYNHDR_ADDR_MSB_OFFSET&#160;&#160;&#160;(XV_HDMITX1_AUX_BASE + (11 * 4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Dynamic HDR Address MSB offset. </p>

</div>
</div>
<a class="anchor" id="af1aa16a7946897669f6883d9f0532cf2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_DYNHDR_PKT_OFFSET&#160;&#160;&#160;(XV_HDMITX1_AUX_BASE + (9 * 4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Dynamic HDR Packet offset. </p>

</div>
</div>
<a class="anchor" id="a1a0133865be039e932ce2e7148d597f6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_DYNHDR_RD_STS_MASK&#160;&#160;&#160;(1 &lt;&lt; 9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Dynamic HDR read response. </p>

</div>
</div>
<a class="anchor" id="a78c4e1ae6b49260a4f3337a7695d28f1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_FSYNC_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC Register offset. </p>

</div>
</div>
<a class="anchor" id="aaa5bed5a9c240264e98a7821cd7d9945"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_FSYNC_PRO_OF&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FYNC PRO Register offset. </p>

</div>
</div>
<a class="anchor" id="a74ffbd378e3b8593508795e42350a66b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Identification * Register offset. </p>

</div>
</div>
<a class="anchor" id="a823088b616d25a73ca25526d6bffd64c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_STA_DSC_PKT_WRRDY_MASK&#160;&#160;&#160;(1 &lt;&lt; 10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status DSC Packet Write Ready. </p>

</div>
</div>
<a class="anchor" id="a79b2893e2ea896e0def9b7b0685a5072"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_STA_DYNHDR_MTW_MASK&#160;&#160;&#160;(1 &lt;&lt; 8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Dynamic HDR MTW started. </p>

</div>
</div>
<a class="anchor" id="a64397a27f0e69610d66f0438c48f7ed4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_STA_FIFO_EMT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Empty mask. </p>

</div>
</div>
<a class="anchor" id="a7bfb37aac0d6dd176a5d5be6e05697d9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_STA_FIFO_FUL_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Full mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a49560390a20d63cec3fd7c79c2f44a76">XV_HdmiTx1_AuxSend()</a>.</p>

</div>
</div>
<a class="anchor" id="af34cd5972f20ed60467569002f116214"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_STA_FREE_PKTS_MASK&#160;&#160;&#160;0x0F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Free Packets mask. </p>

</div>
</div>
<a class="anchor" id="a423f1fbdc32c8f7873cba83c18b36547"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_STA_FREE_PKTS_SHIFT&#160;&#160;&#160;15</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Free Packets shift. </p>

</div>
</div>
<a class="anchor" id="a7add990341b3e99c486abdb4e730c5e2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1__intr_8c.html#a1fde82d7e35ed99e6842e1f33ba09a3b">XV_HdmiTx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a14dcc9b57dc6ff4a5d43c9df86e54723"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a49560390a20d63cec3fd7c79c2f44a76">XV_HdmiTx1_AuxSend()</a>, and <a class="el" href="xv__hdmitx1__intr_8c.html#a1fde82d7e35ed99e6842e1f33ba09a3b">XV_HdmiTx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a778b10c4ff90127e6787100a6836a791"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_STA_PKT_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a49560390a20d63cec3fd7c79c2f44a76">XV_HdmiTx1_AuxSend()</a>.</p>

</div>
</div>
<a class="anchor" id="ac512408565b031446c94da5f6a1d723d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_AUX_VTEM_OFFSET&#160;&#160;&#160;((XV_HDMITX1_AUX_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX VTEM Register offset. </p>

</div>
</div>
<a class="anchor" id="a2195c02fc0a553e5d93885bb80cd5eec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_BRDG_FIFO_LVL_MAX_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 0 LTP mask. </p>

</div>
</div>
<a class="anchor" id="aee51c6675f80c84d891efc77e38bf62f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_BRDG_FIFO_LVL_MAX_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 0 LTP shift. </p>

</div>
</div>
<a class="anchor" id="a7ce238ad43ce93c151d321b928b6909b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_BRDG_FIFO_LVL_MIN_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 0 LTP mask. </p>

</div>
</div>
<a class="anchor" id="a43fbaa6f6970e192e63f4e76beb2aea2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_BRDG_FIFO_LVL_MIN_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 0 LTP shift. </p>

</div>
</div>
<a class="anchor" id="a3e73d02ee219e0a9c53925f60651ed78"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_BRDG_FIFO_LVL_OFFSET&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bridge FIFO Level Register offset. </p>

</div>
</div>
<a class="anchor" id="a5f8f27b07f3e43e7bf04c5bda2e1179f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_CONNECT_CONF_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(15*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO HPD Config. </p>
<ul>
<li>Register offset </li>
</ul>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a4839aca0ca1a11f8b1553026a33d8e6e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_DBG_STS_OFFSET&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Debug Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a3f2aff1ffd776d4097f3d610f92f1083"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_CFG_1_FRL_RATE_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VER (Version Interface) peripheral register offsets. </p>
<p>The VER is the first peripheral on the local bus </p>

</div>
</div>
<a class="anchor" id="a96820760e1aae244998532830dd393fa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_CMD_OFFSET&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Command Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8c.html#a199e2e62f3ebaa5993d935bf2bde0462">XV_HdmiTx1_DdcWriteCommand()</a>.</p>

</div>
</div>
<a class="anchor" id="a7c6cd9c2d19d95db83b737e22375377a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_CMD_RD_TOKEN&#160;&#160;&#160;(0x102)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Read token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>.</p>

</div>
</div>
<a class="anchor" id="ac055e0da09799cd2bf1deaaf7d594a9b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_CMD_STP_TOKEN&#160;&#160;&#160;(0x101)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stop token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

</div>
</div>
<a class="anchor" id="a845b5618c93a1561f1a0a14c8f3eff8e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_CMD_STR_TOKEN&#160;&#160;&#160;(0x100)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Start token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

</div>
</div>
<a class="anchor" id="a138fe51f7ce3717cfaf38b3a67098566"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_CMD_WR_TOKEN&#160;&#160;&#160;(0x103)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Write token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

</div>
</div>
<a class="anchor" id="ac2f786b3061b4df4c53544b6e90f9644"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_CTRL_CLK_DIV_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Clock Divider mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a0304469fda5cb9070c1c0db0c229f11c">XV_HdmiTx1_DdcInit()</a>.</p>

</div>
</div>
<a class="anchor" id="a09105460882cbec545e9ef4fa49b72ae"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Clear * offset. </p>

</div>
</div>
<a class="anchor" id="a5eb95f04ded48dfbc6d9b1895d86ba6e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a446a4adab4ed3b06eb0834191bfa15d9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a0304469fda5cb9070c1c0db0c229f11c">XV_HdmiTx1_DdcInit()</a>, <a class="el" href="xv__hdmitx1_8c.html#a0320f379245cb86d83f5eb565adf6ad8">XV_HdmiTx1_DdcReadData()</a>, <a class="el" href="xv__hdmitx1_8c.html#a12496535333a1068fef5929b566faf5a">XV_HdmiTx1_DdcWaitForDone()</a>, and <a class="el" href="xv__hdmitx1_8c.html#a199e2e62f3ebaa5993d935bf2bde0462">XV_HdmiTx1_DdcWriteCommand()</a>.</p>

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<a class="anchor" id="a7ff97e413ac155c87891bc822fa79213"></a>
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          <td class="memname">#define XV_HDMITX1_DDC_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Run mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8c.html#a0320f379245cb86d83f5eb565adf6ad8">XV_HdmiTx1_DdcReadData()</a>, <a class="el" href="xv__hdmitx1_8c.html#a12496535333a1068fef5929b566faf5a">XV_HdmiTx1_DdcWaitForDone()</a>, and <a class="el" href="xv__hdmitx1_8c.html#a199e2e62f3ebaa5993d935bf2bde0462">XV_HdmiTx1_DdcWriteCommand()</a>.</p>

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<a class="anchor" id="a07043f2b7e7ddb3ba0f27b893e938ed2"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Set * offset. </p>

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<a class="anchor" id="a859fcc36dfd9528cb0cf13e2053fefd1"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_CTRL_TO_STOP_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control TO Stop mask. </p>

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<a class="anchor" id="afaa80a0d738dde8b78bf9eff80002872"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_DAT_OFFSET&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Data Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8c.html#a0320f379245cb86d83f5eb565adf6ad8">XV_HdmiTx1_DdcReadData()</a>.</p>

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<a class="anchor" id="a2fd4e57b08325f9c9b9a65efa90866cf"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Identification * Register offset. </p>

</div>
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<a class="anchor" id="abd120880a6b21ffa91223cb6c3e77af2"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_SINK_VER_REG&#160;&#160;&#160;0x01</td>
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<p>&lt; DDC Register Address </p>

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<a class="anchor" id="a7a18917060714340b40a33de19976226"></a>
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          <td class="memname">#define XV_HDMITX1_DDC_STA_ACK_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status ACK mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8c.html#a76353bf20bfbb1f162c56117c2f71b59">XV_HdmiTx1_DdcGetAck()</a>.</p>

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<a class="anchor" id="afbe726446602f7316ba9f98aabf0541f"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_BUSY_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Busy mask. </p>

</div>
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<a class="anchor" id="a332860dddbc7497d6cf29f5d9fd7b247"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_CMD_FULL&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Command fifo full. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8c.html#a199e2e62f3ebaa5993d935bf2bde0462">XV_HdmiTx1_DdcWriteCommand()</a>.</p>

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<a class="anchor" id="a5b8cad2a23958c491543b26339bf1476"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_CMD_WRDS_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
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<p>Command fifo words mask. </p>

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<a class="anchor" id="a76f3d0e0be126d1b261c496067ef61ee"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_CMD_WRDS_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Command fifo words shift. </p>

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<a class="anchor" id="af92b02d943db10c03bd66537c4b73e3d"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_DAT_EMPTY&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data fifo empty. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8c.html#a0320f379245cb86d83f5eb565adf6ad8">XV_HdmiTx1_DdcReadData()</a>.</p>

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</div>
<a class="anchor" id="a657d709c24bab4058ec2172a8ffcb056"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_DAT_WRDS_MASK&#160;&#160;&#160;0xFF</td>
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      </table>
</div><div class="memdoc">

<p>Data fifo words mask. </p>

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<a class="anchor" id="aa18c60108ec297b2f5cb6d201bb880ad"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_DAT_WRDS_SHIFT&#160;&#160;&#160;24</td>
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      </table>
</div><div class="memdoc">

<p>Data fifo words shift. </p>

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<a class="anchor" id="a0e2070bd8eb10e5ab04afd78224a7c7f"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_DONE_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Busy mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8c.html#a12496535333a1068fef5929b566faf5a">XV_HdmiTx1_DdcWaitForDone()</a>.</p>

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<a class="anchor" id="a13677e2d21fd6fda67136dde0657b511"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Event mask. </p>

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<a class="anchor" id="a74458333d15b366f123b04bb3fa44042"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status IRQ mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1__intr_8c.html#a1fde82d7e35ed99e6842e1f33ba09a3b">XV_HdmiTx1_IntrHandler()</a>.</p>

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</div>
<a class="anchor" id="a76a8d1762bfc7aafed3ae667630f47d6"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX1_DDC_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX1_DDC_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8c.html#a76353bf20bfbb1f162c56117c2f71b59">XV_HdmiTx1_DdcGetAck()</a>, <a class="el" href="xv__hdmitx1_8c.html#a0320f379245cb86d83f5eb565adf6ad8">XV_HdmiTx1_DdcReadData()</a>, <a class="el" href="xv__hdmitx1_8c.html#a12496535333a1068fef5929b566faf5a">XV_HdmiTx1_DdcWaitForDone()</a>, <a class="el" href="xv__hdmitx1_8c.html#a199e2e62f3ebaa5993d935bf2bde0462">XV_HdmiTx1_DdcWriteCommand()</a>, and <a class="el" href="xv__hdmitx1__intr_8c.html#a1fde82d7e35ed99e6842e1f33ba09a3b">XV_HdmiTx1_IntrHandler()</a>.</p>

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<a class="anchor" id="ab727e3b036b6253c5ce50aa6a219c203"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_SCL_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC State of SCL Input mask. </p>

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<a class="anchor" id="aac90959218c9a9cf4c414d457508182f"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_SDA_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
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      </table>
</div><div class="memdoc">

<p>DDC State of SDA Input mask. </p>

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<a class="anchor" id="aa139f217587a626986768317c2efb5e3"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_DDC_STA_TIMEOUT_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
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      </table>
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<p>DDC Status Timeout mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8c.html#a12496535333a1068fef5929b566faf5a">XV_HdmiTx1_DdcWaitForDone()</a>.</p>

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<a class="anchor" id="a4106f7902fe789c40042b05956e9ee39"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_FRL_ACT_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Active mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#adffdae706dbe4333e7f81664ccf0fd22">XV_HdmiTx1_SetFrlActive()</a>.</p>

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</div>
<a class="anchor" id="aa5da06390a2ac2dc17a7581c3cc7f81a"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(3*4))</td>
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      </table>
</div><div class="memdoc">

<p>FRL Control Register Clear offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8c3339f7859efd76ec6a3ee262e20caa">XV_HdmiTx1_FrlExtVidCkeSource()</a>, <a class="el" href="xv__hdmitx1_8h.html#a552e68759230c18b75c2d5510b556488">XV_HdmiTx1_FrlModeEn()</a>, <a class="el" href="xv__hdmitx1_8h.html#a9ae3d651a0d9b2258415a0fcd243ee0c">XV_HdmiTx1_FrlReset()</a>, <a class="el" href="xv__hdmitx1_8h.html#adffdae706dbe4333e7f81664ccf0fd22">XV_HdmiTx1_SetFrlActive()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a36c5a2a45c4aabd06c2e7fbdf26bb991">XV_HdmiTx1_SetFrlLanes()</a>.</p>

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<a class="anchor" id="a6e9c4eff210d0862e3e7ca94bf7fa0e6"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_FRL_CTRL_EXEC_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
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<p>FRL execute mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8f3afde27c63f277de13d600ae3118ef">XV_HdmiTx1_FrlExecute()</a>.</p>

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<a class="anchor" id="a143c3655dacc300a41dac7cbe34c4ed7"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Interrupt Enable mask. </p>

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<a class="anchor" id="a5fe062b0a3114ac13ab10e99fd02dcd3"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_FRL_CTRL_LN_OP_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane Operation mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a36c5a2a45c4aabd06c2e7fbdf26bb991">XV_HdmiTx1_SetFrlLanes()</a>.</p>

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<a class="anchor" id="abc06f99f814e758f194f5afab57fd7e1"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ada8afa970cedeaafee37bffd18b75f87">XV_HdmiTx1_SetFrlLtp()</a>.</p>

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<a class="anchor" id="af14a628baf787a604f23d2114b5ef16a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_CTRL_OP_MODE_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Operation Mode mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a552e68759230c18b75c2d5510b556488">XV_HdmiTx1_FrlModeEn()</a>.</p>

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<a class="anchor" id="af0adeaa6e6dbbf9da1aa465dbe5801c8"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_FRL_CTRL_RSTN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
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<p>FRL Control Resetn mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a9ae3d651a0d9b2258415a0fcd243ee0c">XV_HdmiTx1_FrlReset()</a>.</p>

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</div>
<a class="anchor" id="ae76270b448224670d8cd9615dbac2091"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Register Set offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8f3afde27c63f277de13d600ae3118ef">XV_HdmiTx1_FrlExecute()</a>, <a class="el" href="xv__hdmitx1_8h.html#a8c3339f7859efd76ec6a3ee262e20caa">XV_HdmiTx1_FrlExtVidCkeSource()</a>, <a class="el" href="xv__hdmitx1_8h.html#a552e68759230c18b75c2d5510b556488">XV_HdmiTx1_FrlModeEn()</a>, <a class="el" href="xv__hdmitx1_8h.html#a9ae3d651a0d9b2258415a0fcd243ee0c">XV_HdmiTx1_FrlReset()</a>, <a class="el" href="xv__hdmitx1_8h.html#adffdae706dbe4333e7f81664ccf0fd22">XV_HdmiTx1_SetFrlActive()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a36c5a2a45c4aabd06c2e7fbdf26bb991">XV_HdmiTx1_SetFrlLanes()</a>.</p>

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<a class="anchor" id="a796e498d647fa273f085bc9a561b32b0"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_FRL_CTRL_TST_RC_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL RC Compress mask. </p>

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</div>
<a class="anchor" id="a97c6f090d853e1c36621b67c0b78472e"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_FRL_DISP_ERR_INJ_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Disparity Error Injector Register offset. </p>

</div>
</div>
<a class="anchor" id="a97c6f090d853e1c36621b67c0b78472e"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_DISP_ERR_INJ_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Disparity Error Injector Register offset. </p>

</div>
</div>
<a class="anchor" id="a91a37eb1ef5f54705a9643b9ff7c8797"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_FEC_ERR_INJ_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL FEC Error Injector Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a7bd42ae44563fd0dc91d40c0dfe8d7c3">XV_HdmiTx1_RegisterDebug()</a>.</p>

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<a class="anchor" id="a91a37eb1ef5f54705a9643b9ff7c8797"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_FEC_ERR_INJ_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL FEC Error Injector Register offset. </p>

</div>
</div>
<a class="anchor" id="aeec6c916c6052f91599bb74debafaee1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="a7a9af7e806864a693da679c6ccffb125"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_LNK_CLK_MASK&#160;&#160;&#160;0xFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Link Clock mask. </p>

</div>
</div>
<a class="anchor" id="abcfb2ad0c96c0240bd2211dba81810d0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_LNK_CLK_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Link Clock Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a7505796b81e52d346f14abb3b1a24bfa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_LTP0_REQ_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 0 LTP mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ada8afa970cedeaafee37bffd18b75f87">XV_HdmiTx1_SetFrlLtp()</a>.</p>

</div>
</div>
<a class="anchor" id="a53c5fc702ac87b8400ece0a29d50177b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_LTP0_REQ_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 0 LTP shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ada8afa970cedeaafee37bffd18b75f87">XV_HdmiTx1_SetFrlLtp()</a>.</p>

</div>
</div>
<a class="anchor" id="aa0d9f55a85e21c40e6ffd24e8435a9e6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_LTP1_REQ_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 1 LTP mask. </p>

</div>
</div>
<a class="anchor" id="a232c20ed50d25e04f96b918341d9855d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_LTP1_REQ_SHIFT&#160;&#160;&#160;12</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 1 LTP shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ada8afa970cedeaafee37bffd18b75f87">XV_HdmiTx1_SetFrlLtp()</a>.</p>

</div>
</div>
<a class="anchor" id="a155553393f06b1a723b3c31398279c1b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_LTP2_REQ_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 2 LTP mask. </p>

</div>
</div>
<a class="anchor" id="a97e4f75036407536b66c397d45f641af"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_LTP2_REQ_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 2 LTP shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ada8afa970cedeaafee37bffd18b75f87">XV_HdmiTx1_SetFrlLtp()</a>.</p>

</div>
</div>
<a class="anchor" id="aaa4c8e59d103740cb1916f20154e2860"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_LTP3_REQ_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 3 LTP mask. </p>

</div>
</div>
<a class="anchor" id="a8809fb1d8b55f999acb54a84945598d2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_LTP3_REQ_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 3 LTP shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ada8afa970cedeaafee37bffd18b75f87">XV_HdmiTx1_SetFrlLtp()</a>.</p>

</div>
</div>
<a class="anchor" id="ab4f48aa33f3800c755542f68a044ee1b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_STA_FRL_RST_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status FRL Reset mask. </p>

</div>
</div>
<a class="anchor" id="aa3e6dcf348fd94a3c350bf239eefee9f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_STA_GB_EP_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Gearbox EP mask. </p>

</div>
</div>
<a class="anchor" id="aefff5c96f7b61d619e959fb994a331e6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_STA_GB_SYNC_ERR_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Gearbox Sync Error mask. </p>

</div>
</div>
<a class="anchor" id="ad6246682008ba157f08ac24f80294eed"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1__intr_8c.html#a1fde82d7e35ed99e6842e1f33ba09a3b">XV_HdmiTx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ab380ac5aacd7ffc41be4c522f4a86b76"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_STA_LNK_CLK_OOS_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Link Clock OOS mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="af69097b14c333e4e03d8934c68e5666a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>, and <a class="el" href="xv__hdmitx1__intr_8c.html#a1fde82d7e35ed99e6842e1f33ba09a3b">XV_HdmiTx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ad4f33b6056280050b315f32f9e1dd9c0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_STA_TMR_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Timer Event mask. </p>

</div>
</div>
<a class="anchor" id="a493218b41f2d420b0c003ba1bcde8dd0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_STA_TMR_ZERO_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Timer Zero mask. </p>

</div>
</div>
<a class="anchor" id="a4fd5e5b43cf47643292c1b384a10defa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_STA_TRIB_RST_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status TRIB Reset mask. </p>

</div>
</div>
<a class="anchor" id="a1a67df2123a9cead20b89e2898d3966f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_STA_VID_CLK_OOS_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Video Clock OOS mask. </p>

</div>
</div>
<a class="anchor" id="a1af817a6e8f37b0a75cf466dd7b2e5c2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_TMR_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Timer Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#abe9d06ce9943cedc448f905806cbc6a2">XV_HdmiTx1_GetFrlTimer()</a>, <a class="el" href="xv__hdmitx1_8h.html#aae90d7c942d0f3c605396316c25ad28e">XV_HdmiTx1_SetFrl10MicroSecondsTimer()</a>, <a class="el" href="xv__hdmitx1_8h.html#a2bf2a40cf27de9db617157942c4f901c">XV_HdmiTx1_SetFrlTimer()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a5c81c3da135fd69e74aa106dadce0ca4">XV_HdmiTx1_SetFrlTimerClockCycles()</a>.</p>

</div>
</div>
<a class="anchor" id="ab43b8614d7ac425f46252b52f4934fe5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_VCKE_EXT_MASK&#160;&#160;&#160;(1&lt;&lt;24)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Lane 3 LTP mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a8c3339f7859efd76ec6a3ee262e20caa">XV_HdmiTx1_FrlExtVidCkeSource()</a>.</p>

</div>
</div>
<a class="anchor" id="a31e6bd2a3c47baf19720a962373e49a9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_VID_CLK_MASK&#160;&#160;&#160;0xFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Video Clock mask. </p>

</div>
</div>
<a class="anchor" id="ae77246dd4776e8a41f7b92c093c4e1a0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_VID_CLK_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Video Clock Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a46be7703d3c31e502bc366ec590b02b3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_VP_FIFO_THRD_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Video Packetizer FIFO Threshold Register offset. </p>

</div>
</div>
<a class="anchor" id="a46be7703d3c31e502bc366ec590b02b3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_VP_FIFO_THRD_OFFSET&#160;&#160;&#160;((XV_HDMITX1_FRL_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Video Packetizer FIFO Threshold Register offset. </p>

</div>
</div>
<a class="anchor" id="a8239e53495feea5050dbda9cad646119"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_HPD_TIMEGRID_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(13*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO HPD Config. </p>
<ul>
<li>offset </li>
</ul>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ae801c2b02c46a84de57bc938dd96c2f9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_HW_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Prevent circular inclusions by using protection macros. </p>

</div>
</div>
<a class="anchor" id="a509f93707c8ca85278312981c1db7974"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx1_In32&#160;&#160;&#160;Xil_In32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Input Operations. </p>

</div>
</div>
<a class="anchor" id="a02751a20bad34eb921ded41ecd6449bd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_MASK_16&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 bit mask value </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx1__selftest_8c.html#af29db67dfae3a2ae507640836c23847a">XV_HdmiTx1_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a20bd10d0de6ddcc5bd6b17b3c7121d65"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_MASK_BLUE_OFFSET&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Blue Component Register offset. </p>

</div>
</div>
<a class="anchor" id="a898ea3e6392a25115f070b6bd759e2c7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_MASK_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="a59eb379430a75238522ae45d39bfb8e7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_MASK_CTRL_NOISE_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Control Noise. </p>

</div>
</div>
<a class="anchor" id="ab6a37549bc9888ef902b62f9f0e30ef1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_MASK_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Control Register offset. </p>

</div>
</div>
<a class="anchor" id="aa76f75af182c527f0837a8e72e07a0ab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_MASK_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Control Run mask. </p>

</div>
</div>
<a class="anchor" id="ac83138bb1465d39d0f80a53700c0b884"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_MASK_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="a1cac6ccd3a3706173ed032c701e14087"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_MASK_GREEN_OFFSET&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Green Component Register offset. </p>

</div>
</div>
<a class="anchor" id="ae0da2131cee32e9acfdbbc3a516af966"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_MASK_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="a15730fa7eed0854af7219fdfecd974c1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_MASK_RED_OFFSET&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Red Component Register offset. </p>

</div>
</div>
<a class="anchor" id="a5bc7d731779d71bbcee75aed8ade8646"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_MASK_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX1_MASK_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Status Register offset. </p>

</div>
</div>
<a class="anchor" id="adc4c9715f4a62bd5213ab32e59feb4de"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx1_Out32&#160;&#160;&#160;Xil_Out32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Output Operations. </p>

</div>
</div>
<a class="anchor" id="ab2c8c843f94dae2bf7b7050da886ee8f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Clear * offset. </p>

</div>
</div>
<a class="anchor" id="a633284b6032afb987ebdc09d68e111a5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="aac3a70c2cfaeaee8e5b85888bcaa38d3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register * offset. </p>

</div>
</div>
<a class="anchor" id="a7dbedee4c4749f3d28da3b493c792cb6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a7b92bd89968718f069ca23ff200f90b0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Set * offset. </p>

</div>
</div>
<a class="anchor" id="a85275d4df3edf2c08d38d544b5928c95"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_ID&#160;&#160;&#160;0x2200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TX's PIO ID. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx1__selftest_8c.html#af29db67dfae3a2ae507640836c23847a">XV_HdmiTx1_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a771c245a4146fa673670d145a49ab42c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Identification * Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx1__selftest_8c.html#af29db67dfae3a2ae507640836c23847a">XV_HdmiTx1_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a47d0be5976cb417367f227882aba616a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_BRDG_LOCKED_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Bridge Locked mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ad7989878b63e6d1ccc17b9fffebdb1e7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_BRDG_OVERFLOW_MASK&#160;&#160;&#160;(1&lt;&lt;10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Bridge Overflow mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a9d53bbc6e4513d332030da84a4d5366c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_BRDG_UNDERFLOW_MASK&#160;&#160;&#160;(1&lt;&lt;11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Bridge Underflow mask. </p>
<p>DDC (Display Data Channel) peripheral register offsets The DDC is the second peripheral on the local bus </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a0840f8be0f908f0ebf7f88da62919041"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_EVT_FE_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(12*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Falling Edge Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="aae6c35fd65f989a9a2002d0b5d1fb456"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_EVT_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Register * offset. </p>

</div>
</div>
<a class="anchor" id="a083e42899636cd5e11e57dc81ed473d1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_EVT_RE_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Rising Edge Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a8e4ab9f93df19e5011f0abc4b62d6d68"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_HPD_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In HPD mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="acaa33be8f32fd160bc231fe83d8e4e7b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_HPD_TOGGLE_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In HPD toggle mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a9c67bb4f654071b9bbd7c0bb57bd431b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_LNK_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In link ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ab20b6e84abcd0378fbc8e17282eacb16"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a0ebc15cfa04faafb28f8ffbf75ae033a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_PPP_MASK&#160;&#160;&#160;0x07</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Pixel packing phase mask. </p>

</div>
</div>
<a class="anchor" id="ada3d9d45b3dfcc1f6ed0bf48ee626a4b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_PPP_SHIFT&#160;&#160;&#160;5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Pixel packing phase shift. </p>

</div>
</div>
<a class="anchor" id="a9535ee8b4bd5af9bd9b91476b2ccfec5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_VID_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In video ready mask. </p>

</div>
</div>
<a class="anchor" id="aa69dc4de1fcc61075bb66a5f72498f09"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_IN_VS_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Vsync mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a648102aabd55a2e9475005867d63dd6e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_BRIDGE_PIXEL_MASK&#160;&#160;&#160;(1&lt;&lt;30)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Bridge_Pixel repeat mask. </p>

</div>
</div>
<a class="anchor" id="afcb960eb73caed51fff7e1028e0d3a11"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_BRIDGE_YUV420_MASK&#160;&#160;&#160;(1&lt;&lt;29)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Bridge_YUV420 mask. </p>

</div>
</div>
<a class="anchor" id="a34819a1c42353de5eec449bc38c93efc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register Clear * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#afad06f0251d19842573b1f2695149e8c">XV_HdmiTx1_ClearGcpAvmuteBit()</a>, <a class="el" href="xv__hdmitx1_8h.html#ae56341f568a34cc9c677f5d8c822e156">XV_HdmiTx1_ClearGcpClearAvmuteBit()</a>, <a class="el" href="xv__hdmitx1_8h.html#a74e6c88c1599a6f0290c5db420bc8d50">XV_HdmiTx1_EXT_SYSRST()</a>, <a class="el" href="xv__hdmitx1_8h.html#a73e17f2ac248affe52270168283ba45f">XV_HdmiTx1_EXT_VRST()</a>, <a class="el" href="xv__hdmitx1_8h.html#aecd47642f9aa91941d14c04543f73827">XV_HdmiTx1_INT_LRST()</a>, and <a class="el" href="xv__hdmitx1_8h.html#adf9e5c73a5f308d04eea85dd4db8f42f">XV_HdmiTx1_INT_VRST()</a>.</p>

</div>
</div>
<a class="anchor" id="a58610b772b050b3a4504d274bd53f09a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_COLOR_DEPTH_MASK&#160;&#160;&#160;0x30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Depth mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a25379b09e782626e79fd3b785b671f2e">XV_HdmiTx1_SetColorDepth()</a>.</p>

</div>
</div>
<a class="anchor" id="a9044e4c1c1a22e9f5540b3e28e164ebe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_COLOR_DEPTH_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Depth shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a25379b09e782626e79fd3b785b671f2e">XV_HdmiTx1_SetColorDepth()</a>.</p>

</div>
</div>
<a class="anchor" id="ac9a6bae49a6bba1d495a19e74aff47d8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_COLOR_SPACE_MASK&#160;&#160;&#160;0xC00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a0aa5bbd57a95785df766d6d5a919479a">XV_HdmiTx1_SetColorFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="aef681ccbd7dad5067f84ef4b7ecdc685"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_COLOR_SPACE_SHIFT&#160;&#160;&#160;10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a0aa5bbd57a95785df766d6d5a919479a">XV_HdmiTx1_SetColorFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="abe4e12802e1167c1761c54d00083dad6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_DYN_HDR_DM_EN_MASK&#160;&#160;&#160;(1 &lt;&lt; 23)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Dynamic HDR Data Mover Enable. </p>

</div>
</div>
<a class="anchor" id="a11a55e987433d85234ed12bbaeae13ad"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_EXT_SYSRST_MASK&#160;&#160;&#160;(1&lt;&lt;22)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out EXT_SYSRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a74e6c88c1599a6f0290c5db420bc8d50">XV_HdmiTx1_EXT_SYSRST()</a>.</p>

</div>
</div>
<a class="anchor" id="a0ef4633d186e31591484e815f99ef471"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_EXT_VRST_MASK&#160;&#160;&#160;(1&lt;&lt;21)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out EXT_VRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a73e17f2ac248affe52270168283ba45f">XV_HdmiTx1_EXT_VRST()</a>.</p>

</div>
</div>
<a class="anchor" id="acdf644126236c17fe0561f8b7b35e848"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_GCP_AVMUTE_MASK&#160;&#160;&#160;(1&lt;&lt;31)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out GCP_AVMUTE mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#afad06f0251d19842573b1f2695149e8c">XV_HdmiTx1_ClearGcpAvmuteBit()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab1fbe68d90e50414180d190c9f4c5a75">XV_HdmiTx1_SetGcpAvmuteBit()</a>.</p>

</div>
</div>
<a class="anchor" id="af12c5bc4580008e386420488c4dc2945"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_GCP_CLEARAVMUTE_MASK&#160;&#160;&#160;(1&lt;&lt;28)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out GCP_CLEARAVMUTE mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae56341f568a34cc9c677f5d8c822e156">XV_HdmiTx1_ClearGcpClearAvmuteBit()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a8052b352068e63f196e7cb4eaba721e1">XV_HdmiTx1_SetGcpClearAvmuteBit()</a>.</p>

</div>
</div>
<a class="anchor" id="ae926811c3ab955754b7e1d34e06c0b30"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_INT_LRST_MASK&#160;&#160;&#160;(1&lt;&lt;20)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out INT_LRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#aecd47642f9aa91941d14c04543f73827">XV_HdmiTx1_INT_LRST()</a>.</p>

</div>
</div>
<a class="anchor" id="abb0a513439f7691a66e0baba33ee7e99"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_PIO_OUT_INT_VRST_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out INT_VRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#adf9e5c73a5f308d04eea85dd4db8f42f">XV_HdmiTx1_INT_VRST()</a>.</p>

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          <td class="memname">#define XV_HDMITX1_PIO_OUT_MODE_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
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<p>PIO Out Mode mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

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<a class="anchor" id="ae9de0ab9551b81695551dd340024f11a"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_OUT_MSK_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(8*4))</td>
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      </table>
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<p>PIO Out Mask Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a25379b09e782626e79fd3b785b671f2e">XV_HdmiTx1_SetColorDepth()</a>, <a class="el" href="xv__hdmitx1_8h.html#a0aa5bbd57a95785df766d6d5a919479a">XV_HdmiTx1_SetColorFormat()</a>, <a class="el" href="xv__hdmitx1_8h.html#a606cf8a2a1153de19c66925b9d462636">XV_HdmiTx1_SetPixelRate()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab1c2a996dc8766605df5df4d6a37eb45">XV_HdmiTx1_SetSampleRate()</a>.</p>

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<a class="anchor" id="aef14faec6d7dec76359597de87c027e1"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_OUT_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(5*4))</td>
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      </table>
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<p>PIO Out Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>, <a class="el" href="xv__hdmitx1_8h.html#a25379b09e782626e79fd3b785b671f2e">XV_HdmiTx1_SetColorDepth()</a>, <a class="el" href="xv__hdmitx1_8h.html#a0aa5bbd57a95785df766d6d5a919479a">XV_HdmiTx1_SetColorFormat()</a>, <a class="el" href="xv__hdmitx1_8h.html#a606cf8a2a1153de19c66925b9d462636">XV_HdmiTx1_SetPixelRate()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab1c2a996dc8766605df5df4d6a37eb45">XV_HdmiTx1_SetSampleRate()</a>.</p>

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<a class="anchor" id="a493cc4bcc9456c6e4b5b7b6f4ef278c7"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_OUT_PIXEL_RATE_MASK&#160;&#160;&#160;0xC0</td>
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<p>PIO Out Pixel Rate mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a606cf8a2a1153de19c66925b9d462636">XV_HdmiTx1_SetPixelRate()</a>.</p>

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<a class="anchor" id="a6fe7c0047c787b5b463931d65a9857aa"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_OUT_PIXEL_RATE_SHIFT&#160;&#160;&#160;6</td>
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      </table>
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<p>PIO Out Pixel Rate shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a606cf8a2a1153de19c66925b9d462636">XV_HdmiTx1_SetPixelRate()</a>.</p>

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<a class="anchor" id="a01feb7322f445f662f190d24c4d82583"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_OUT_RST_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
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      </table>
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<p>PIO Out Reset mask. </p>

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<a class="anchor" id="a36e3a208b0ef9f5385c89a994916c49c"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_OUT_SAMPLE_RATE_MASK&#160;&#160;&#160;0x300</td>
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      </table>
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<p>PIO Out Sample Rate mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab1c2a996dc8766605df5df4d6a37eb45">XV_HdmiTx1_SetSampleRate()</a>.</p>

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<a class="anchor" id="ab23dda9e51f0e85b00f859790bce3ad4"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_OUT_SAMPLE_RATE_SHIFT&#160;&#160;&#160;8</td>
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<p>PIO Out Sample Rate shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab1c2a996dc8766605df5df4d6a37eb45">XV_HdmiTx1_SetSampleRate()</a>.</p>

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<a class="anchor" id="aa6ac2799e1faa5133f3ab35018aba54d"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_OUT_SCRM_MASK&#160;&#160;&#160;(1&lt;&lt;12)</td>
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      </table>
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<p>PIO Out Scrambler mask. </p>

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<a class="anchor" id="a916d49f0a22d9ef6e369ff80353e00af"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_OUT_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(6*4))</td>
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<p>PIO Out Register Set * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a74e6c88c1599a6f0290c5db420bc8d50">XV_HdmiTx1_EXT_SYSRST()</a>, <a class="el" href="xv__hdmitx1_8h.html#a73e17f2ac248affe52270168283ba45f">XV_HdmiTx1_EXT_VRST()</a>, <a class="el" href="xv__hdmitx1_8h.html#aecd47642f9aa91941d14c04543f73827">XV_HdmiTx1_INT_LRST()</a>, <a class="el" href="xv__hdmitx1_8h.html#adf9e5c73a5f308d04eea85dd4db8f42f">XV_HdmiTx1_INT_VRST()</a>, <a class="el" href="xv__hdmitx1_8h.html#ab1fbe68d90e50414180d190c9f4c5a75">XV_HdmiTx1_SetGcpAvmuteBit()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a8052b352068e63f196e7cb4eaba721e1">XV_HdmiTx1_SetGcpClearAvmuteBit()</a>.</p>

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<a class="anchor" id="a77a89d53c2da8e5b11717d4ddb29da32"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
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<p>PIO Status Event mask. </p>

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<a class="anchor" id="ab68b9045690c17f85d3d454f182aaaa4"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
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<p>PIO Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1__intr_8c.html#a1fde82d7e35ed99e6842e1f33ba09a3b">XV_HdmiTx1_IntrHandler()</a>.</p>

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<a class="anchor" id="aad716fe9cadcb6ad07df46c18b0f67d9"></a>
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          <td class="memname">#define XV_HDMITX1_PIO_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(4*4))</td>
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<p>PIO Status Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1__intr_8c.html#a1fde82d7e35ed99e6842e1f33ba09a3b">XV_HdmiTx1_IntrHandler()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmitx1__hw_8h.html#a509f93707c8ca85278312981c1db7974">XV_HdmiTx1_In32</a>((BaseAddress) + (RegOffset))</td>
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<p>This macro reads a value from a HDMI TX register. </p>
<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI TX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b" title="This macro reads a value from a HDMI TX register. ">XV_HdmiTx1_ReadReg(UINTPTR BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a49560390a20d63cec3fd7c79c2f44a76">XV_HdmiTx1_AuxSend()</a>, <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, <a class="el" href="xv__hdmitx1_8c.html#a76353bf20bfbb1f162c56117c2f71b59">XV_HdmiTx1_DdcGetAck()</a>, <a class="el" href="xv__hdmitx1_8c.html#a0320f379245cb86d83f5eb565adf6ad8">XV_HdmiTx1_DdcReadData()</a>, <a class="el" href="xv__hdmitx1_8c.html#a12496535333a1068fef5929b566faf5a">XV_HdmiTx1_DdcWaitForDone()</a>, <a class="el" href="xv__hdmitx1_8c.html#a199e2e62f3ebaa5993d935bf2bde0462">XV_HdmiTx1_DdcWriteCommand()</a>, <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>, <a class="el" href="xv__hdmitx1_8h.html#ae2022f3a37591ca01f2028e0e938e331">XV_HdmiTx1_GetAudioFormat()</a>, <a class="el" href="xv__hdmitx1_8h.html#abe9d06ce9943cedc448f905806cbc6a2">XV_HdmiTx1_GetFrlTimer()</a>, <a class="el" href="xv__hdmitx1__intr_8c.html#a1fde82d7e35ed99e6842e1f33ba09a3b">XV_HdmiTx1_IntrHandler()</a>, <a class="el" href="xv__hdmitx1_8h.html#a7bd42ae44563fd0dc91d40c0dfe8d7c3">XV_HdmiTx1_RegisterDebug()</a>, <a class="el" href="xv__hdmitx1__selftest_8c.html#af29db67dfae3a2ae507640836c23847a">XV_HdmiTx1_SelfTest()</a>, <a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels()</a>, <a class="el" href="xv__hdmitx1_8h.html#a23a20e6c1144064686e03fd0650ec46f">XV_HdmiTx1_SetAudioFormat()</a>, <a class="el" href="xv__hdmitx1_8h.html#ada8afa970cedeaafee37bffd18b75f87">XV_HdmiTx1_SetFrlLtp()</a>, <a class="el" href="xv__hdmitx1_8h.html#a937b182eae5d5d5eefe0e7cbc0e833c7">XV_HdmiTxSs1_GetAudioCtsVal()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a58b5302d9843f58fcf1336d2a0ab9bcd">XV_HdmiTxSs1_GetAudioNVal()</a>.</p>

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<a class="anchor" id="a52b7d366cc179f1aa90b20ae9ed5a6de"></a>
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<p>16 shift value </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx1__selftest_8c.html#af29db67dfae3a2ae507640836c23847a">XV_HdmiTx1_SelfTest()</a>.</p>

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<a class="anchor" id="a3154f6e901d66ba2320ccf5ab4d08821"></a>
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          <td class="memname">#define XV_HDMITX1_TOGGLE_CONF_OFFSET&#160;&#160;&#160;((XV_HDMITX1_PIO_BASE)+(14*4))</td>
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      </table>
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<p>PIO HPD Config. </p>
<ul>
<li>Register offset </li>
</ul>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a2a61ed968e178ed839d00ed19855ded3"></a>
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          <td class="memname">#define XV_HDMITX1_VCKE_SYS_CNT_OFFSET&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(3*4))</td>
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<p>VCKE System Count Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

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<a class="anchor" id="acdb9781981b55f2a70cf2ef4e50e00cb"></a>
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          <td class="memname">#define XV_HDMITX1_VER_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(0*4))</td>
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<p>VER Identification * Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

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<a class="anchor" id="ab85b13706cb38b267c66b44d3533e000"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX1_VER_VERSION_OFFSET&#160;&#160;&#160;((XV_HDMITX1_VER_BASE)+(1*4))</td>
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<p>VER Version Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo()</a>.</p>

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<a class="anchor" id="af4ba16c8e4e0505aa1e7ea79d06eb2d4"></a>
<div class="memitem">
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          <td class="memname">#define XV_HdmiTx1_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmitx1__hw_8h.html#adc4c9715f4a62bd5213ab32e59feb4de">XV_HdmiTx1_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro writes a value to a HDMI TX register. </p>
<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI TX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4" title="This macro writes a value to a HDMI TX register. ">XV_HdmiTx1_WriteReg(UINTPTR BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae842f2e11b05dbc07382f202bffbf7ea">XV_HdmiTx1_AudioEnable()</a>, <a class="el" href="xv__hdmitx1_8h.html#afaf9e97accf4f26abbdac8ef9410dcab">XV_HdmiTx1_Aux_Dsc_Send_Data()</a>, <a class="el" href="xv__hdmitx1_8h.html#a0ac2f0429e283d420ab2498273c288a4">XV_HdmiTx1_Aux_Dsc_Send_Header()</a>, <a class="el" href="xv__hdmitx1_8h.html#a1b7d74b3288271064644bda7857a1c8b">XV_HdmiTx1_AuxEnable()</a>, <a class="el" href="xv__hdmitx1_8h.html#a49560390a20d63cec3fd7c79c2f44a76">XV_HdmiTx1_AuxSend()</a>, <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, <a class="el" href="xv__hdmitx1_8h.html#afad06f0251d19842573b1f2695149e8c">XV_HdmiTx1_ClearGcpAvmuteBit()</a>, <a class="el" href="xv__hdmitx1_8h.html#ae56341f568a34cc9c677f5d8c822e156">XV_HdmiTx1_ClearGcpClearAvmuteBit()</a>, <a class="el" href="xv__hdmitx1_8h.html#a0304469fda5cb9070c1c0db0c229f11c">XV_HdmiTx1_DdcInit()</a>, <a class="el" href="xv__hdmitx1_8c.html#a12496535333a1068fef5929b566faf5a">XV_HdmiTx1_DdcWaitForDone()</a>, <a class="el" href="xv__hdmitx1_8c.html#a199e2e62f3ebaa5993d935bf2bde0462">XV_HdmiTx1_DdcWriteCommand()</a>, <a class="el" href="xv__hdmitx1_8h.html#a74e6c88c1599a6f0290c5db420bc8d50">XV_HdmiTx1_EXT_SYSRST()</a>, <a class="el" href="xv__hdmitx1_8h.html#a73e17f2ac248affe52270168283ba45f">XV_HdmiTx1_EXT_VRST()</a>, <a class="el" href="xv__hdmitx1_8h.html#ad22b60a3d798ee469dcc71a04100843d">XV_HdmiTx1_FRLACRStart()</a>, <a class="el" href="xv__hdmitx1_8h.html#a8f3afde27c63f277de13d600ae3118ef">XV_HdmiTx1_FrlExecute()</a>, <a class="el" href="xv__hdmitx1_8h.html#a8c3339f7859efd76ec6a3ee262e20caa">XV_HdmiTx1_FrlExtVidCkeSource()</a>, <a class="el" href="xv__hdmitx1_8h.html#a552e68759230c18b75c2d5510b556488">XV_HdmiTx1_FrlModeEn()</a>, <a class="el" href="xv__hdmitx1_8h.html#a9ae3d651a0d9b2258415a0fcd243ee0c">XV_HdmiTx1_FrlReset()</a>, <a class="el" href="xv__hdmitx1_8h.html#aecd47642f9aa91941d14c04543f73827">XV_HdmiTx1_INT_LRST()</a>, <a class="el" href="xv__hdmitx1_8h.html#adf9e5c73a5f308d04eea85dd4db8f42f">XV_HdmiTx1_INT_VRST()</a>, <a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels()</a>, <a class="el" href="xv__hdmitx1_8h.html#a23a20e6c1144064686e03fd0650ec46f">XV_HdmiTx1_SetAudioFormat()</a>, <a class="el" href="xv__hdmitx1_8h.html#a25379b09e782626e79fd3b785b671f2e">XV_HdmiTx1_SetColorDepth()</a>, <a class="el" href="xv__hdmitx1_8h.html#a0aa5bbd57a95785df766d6d5a919479a">XV_HdmiTx1_SetColorFormat()</a>, <a class="el" href="xv__hdmitx1_8h.html#aae90d7c942d0f3c605396316c25ad28e">XV_HdmiTx1_SetFrl10MicroSecondsTimer()</a>, <a class="el" href="xv__hdmitx1_8h.html#adffdae706dbe4333e7f81664ccf0fd22">XV_HdmiTx1_SetFrlActive()</a>, <a class="el" href="xv__hdmitx1_8h.html#a36c5a2a45c4aabd06c2e7fbdf26bb991">XV_HdmiTx1_SetFrlLanes()</a>, <a class="el" href="xv__hdmitx1_8h.html#ada8afa970cedeaafee37bffd18b75f87">XV_HdmiTx1_SetFrlLtp()</a>, <a class="el" href="xv__hdmitx1_8h.html#a2bf2a40cf27de9db617157942c4f901c">XV_HdmiTx1_SetFrlTimer()</a>, <a class="el" href="xv__hdmitx1_8h.html#a5c81c3da135fd69e74aa106dadce0ca4">XV_HdmiTx1_SetFrlTimerClockCycles()</a>, <a class="el" href="xv__hdmitx1_8h.html#ab1fbe68d90e50414180d190c9f4c5a75">XV_HdmiTx1_SetGcpAvmuteBit()</a>, <a class="el" href="xv__hdmitx1_8h.html#a8052b352068e63f196e7cb4eaba721e1">XV_HdmiTx1_SetGcpClearAvmuteBit()</a>, <a class="el" href="xv__hdmitx1_8h.html#a606cf8a2a1153de19c66925b9d462636">XV_HdmiTx1_SetPixelRate()</a>, <a class="el" href="xv__hdmitx1_8h.html#ab1c2a996dc8766605df5df4d6a37eb45">XV_HdmiTx1_SetSampleRate()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a7f1498e69d193cbd626999414e863558">XV_HdmiTx1_TMDSACRStart()</a>.</p>

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